поискавой системы для электроныых деталей |
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UC3825B датащи(PDF) 8 Page - Texas Instruments |
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UC3825B датащи(HTML) 8 Page - Texas Instruments |
8 / 9 page 8 GROUND PLANES Each output driver of these devices is capable of 2A peak currents. Careful layout is essential for correct operation of the chip. A ground plane must be employed. A unique sec- tion of the ground plane must be designated for high di/dt currents associated with the output stages. This point is the power ground to which the PGND pin is connected. Power ground can be separated from the rest of the ground plane and connected at a single point, although this is not strictly necessary if the high di/dt paths are well understood and accounted for. VCC should be bypassed directly to power ground with a good high frequency capacitor. The sources UC1823A,B/1825A,B UC2823A,B/2825A,B UC3823A,B/3825A,B of the power MOSFET should connect to power ground as should the return connection for input power to the sys- tem and the bulk input capacitor. The output should be clamped with a high current Schottky diode to both VCC and PGND. Nothing else should be connected to power ground. VREF should be bypassed directly to the signal portion of the ground plane with a good high frequency capaci- tor. Low ESR/ESL ceramic 1 µF capacitors are recom- mended for both VCC and VREF. All analog circuitry should likewise be bypassed to the signal ground plane. APPLICATIONS INFORMATION (cont.) UDG-95115 UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL.(603) 424-2410 • FAX (603) 424-3460 grounding and bypass procedures should be followed. The use of a ground plane is highly recommended. Open Loop Test Circuit This test fixture is useful for exercising many of the UC3823A,B, UC3825A,B functions and measuring their specifications. As with any wideband circuit, careful UDG-95116 |
Аналогичный номер детали - UC3825B |
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Аналогичное описание - UC3825B |
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