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U2794B датащи(PDF) 5 Page - ATMEL Corporation |
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U2794B датащи(HTML) 5 Page - ATMEL Corporation |
5 / 15 page 5 U2794B 4653C–CELL–06/03 3.2 “Power DOWN” 14 V POFF 1V D 4 LO Input, LO in 4.1 Frequency range 17 f iLO 70 1000 MHz D 4.2 Input level (2) 17 P iLO -12 -10 -5 dBm D 4.3 Input impedance See Figure 12 17 Z iLO 50 W D 4.4 Voltage standing wave ratio See Figure 5 17 VSWR LO 1.2 2 D 4.5 Duty-cycle range 17 DCR LO 0.4 0.6 D 5 RF Input, RF in 5.1 Noise figure (DSB) symmetrical output at 950 MHz (3) at 100 MHz 7, 8 NF 12 10 dB D 5.2 Frequency range f iRF = FiLO ± BWYQ 7, 8 f iRF 40 1030 MHz D 5.3 -1 dB input compression point High gain Low gain 7, 8 P 1dBHG P 1dBLG -8 +3.5 dBm D 5.4 Second order IIP (4) 7, 8 IIP 2HG 35 dBm D 5.5 Third order IIP High gain Low gain 7, 8 IIP 3HG IIP 3LG +3 +13 dBm D 5.6 LO leakage Symmetric input Asymmetric input 7, 8 L OL £ -60 £ -55 dBm D 5.7 Input impedance see Figure 12 7, 8 ZiRF 500II0.8 WIIpF D 6 I/Q Outputs (I, IX, Q, QX) Emitter Follower I = 0.6 mA 6.1 3–dB bandwidth w/o external C 1, 2, 19, 20 BWI/Q ³ 30 MHz D 6.2 I/Q amplitude error 1, 2, 19, 20 Ae -0.5 £ ±0.2 +0.5 dB B 6.3 I/Q phase error 1, 2, 19, 20 Pe -3 £ ±1.5 +3 Deg B Electrical Characteristics (Continued) Test conditions (unless otherwise specified); VS = 5 V, Tamb = 25°C, referred to test circuit System impedance ZO = 50 W, fiLO = 950 MHz, PiLO = -10 dBm No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. During power-down status a load circuitry with DC-isolation to GND is assumed, otherwise a current of I » (VS -0.8 V)/RI has to be added to the above power-down current for each output I, IX, Q, QX. 2. The required LO-Level is a function of the LO frequency (see Figure 8). 3. Measured with input matching. For 950 MHz, the optional transmission line T3 at the RF input may be used for this pur- pose. Noise figure measurements without using the differential output signal result in a worse noise figure. 4. Using Pins 7 and 8 as a symmetric RF input, the second-order IIP can be improved. 5. Due to test board parasitics, this bandwidth may be reduced and not be equal for I, IX, Q, QX. If symmetry and full band- width is required, the lowpass Pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the I/Q outputs can be increased further by using a resistor between Pins 3, 4, 9 and 10. These resistors shunt the internal loads of RI ~ 5.4 k W. The decrease in gain here has to be considered. 6. The internal current of the output emitter followers is 0.6 mA. This reduces the undistorted output voltage swing at a 50 W load to approsimately 30 mV. For low signal distortion the load impedance should be RI ³ 5 kW. 7. Referred to the level of the output vector 8. The low-gain status is achieved with an open or high-ohmic Pin 11. A recommended application circuit for switching between high and low gain status is hown in Figure 3. I 2 Q 2 + |
Аналогичный номер детали - U2794B_97 |
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Аналогичное описание - U2794B_97 |
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