74V2G74

2/13

INPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

TRUTH TABLE

X= Don’t care

LOGIC DIAGRAM

This logic diagram has not be used to estimate propagation delays

PIN No

SYMBOL

NAME AND FUNCTION

6CLR

Asyncronous Reset -

Direct Input

2

D

Data Input

1

CK

Clock Input

(LOW to HIGH, Edge

Triggered)

7PR

Asyncronous Set - Direct

Input

5

Q

True Flip-Flop Output

3Q

Complement Flip-Flop

Output

4

GND

Ground (0V)

Positive Supply Voltage

INPUTS

OUTPUTS

FUNCTION

CLR

PR

DCK

Q

Q

L

H

X

X

L

H

CLEAR

H

L

X

X

H

L

PRESET

LL

X

X

H

H

HH

L

L

H

HHH

H

L

HH

X

NO CHANGE