AD5415

Rev. 0 | Page 6 of 28

DB15

(N)

DB15

(N+1)

DB0

(N)

DB0

(N+1)

DB15

(N)

DB0

(N)

SCLK

SYNC

SDIN

SDO

ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS

DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING

EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.

Figure 3. Daisy-Chain and Readback Modes Timing Diagram

200

µAI

OL

200

µAI

OH

TO OUTPUT

PIN

50pF

2

Figure 4. Load Circuit for SDO Timing Specifications