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CY7C1444KV33 датащи(PDF) 5 Page - Cypress Semiconductor

номер детали CY7C1444KV33
подробное описание детали  36-Mbit (1M36/2M18) Pipelined DCD Sync SRAM
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производитель  CYPRESS [Cypress Semiconductor]
домашняя страница  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

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CY7C1444KV33
CY7C1445KV33
Document Number: 001-66678 Rev. *G
Page 5 of 22
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-synchronous
Address inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled
active. A1: A0 are fed to the two-bit counter..
BWA, BWB, BWC, BWD Input-synchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK.
GW
Input-synchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of
CLK, a global write is conducted (all bytes are written, regardless of the values on BWX
and BWE).
BWE
Input-synchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
CLK
Input-clock
Clock input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
CE1
Input-synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1
is HIGH. CE1 is sampled only when a new external address is loaded.
CE2
Input-synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device. CE2is sampled only when
a new external address is loaded.
CE3
Input-synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device. CE3 is sampled only when
a new external address is loaded.
OE
Input-asynchronous
Output enable, asynchronous input, active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ pins
are tristated, and act as input data pins. OE is masked during the first clock of a read
cycle when emerging from a deselected state.
ADV
Input-synchronous
Advance input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.
ADSP
Input-synchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted
HIGH.
ADSC
Input-synchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
ZZ
Input-asynchronous
ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs, DQPs
I/O-synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave
as outputs. When HIGH, DQs and DQPX are placed in a tristate condition.
VDD
Power supply
Power supply inputs to the core of the device.
VSS
Ground
Ground for the core of the device.
VSSQ
I/O ground
Ground for the I/O circuitry.


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