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74LVC1G175 датащи(PDF) 1 Page - NXP Semiconductors |
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74LVC1G175 датащи(HTML) 1 Page - NXP Semiconductors |
1 / 17 page 1. General description The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC1G175 is a single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall times. 2. Features s Wide supply voltage range from 1.65 V to 5.5 V s 5 V tolerant inputs for interfacing with 5 V logic s High noise immunity s Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8B/JESD36 (2.7 V to 3.6 V). s ±24 mA output drive (V CC = 3.0 V) s ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s CMOS low power consumption s Latch-up performance exceeds 250 mA s Direct interface with TTL levels s Inputs accept voltages up to 5 V s Multiple package options s Specified from −40 °Cto+85 °C and −40 °C to +125 °C. 74LVC1G175 Single D-type flip-flop with reset; positive-edge trigger Rev. 01 — 18 October 2004 Product data sheet |
Аналогичный номер детали - 74LVC1G175 |
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Аналогичное описание - 74LVC1G175 |
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