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LTM4639 датащи(PDF) 7 Page - Linear Technology

номер детали LTM4639
подробное описание детали  Ultrathin, Triple Output, Step-Down 關Module Regulator for DDR-QDR4 Memory
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производитель  LINER [Linear Technology]
домашняя страница  http://www.linear.com
Logo LINER - Linear Technology

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LTM4632
7
4632fc
For more information www.linear.com/LTM4632
PIN FUNCTIONS
VIN (A2, B3, D3, E2): Power Input Pins. Apply input
voltage between these pins and GND pins. Recommend
placing input decoupling capacitance directly between VIN
pins and GND pins.
VOUT1 (D1, E1), VOUT2 (A1, B1): Power Output Pins of
each Switching Mode Regulator. Apply output load be-
tween these pins and GND pins. Recommend placing out-
put decoupling capacitance directly between these pins
and GND pins.
GND (C1-C2, C4, B5, D5): Power Ground Pins for Both
Input and Output Returns.
PGOOD1 (D4): Output Power Good with Open-Drain Logic
of the Channel 1 Switching Mode Regulator. PGOOD1 is
pulled to ground when the voltage on the FB1 pin is not
within ±8% (typical) of the internal 0.6V reference. This
threshold has 15mV of hysteresis.
PGOOD2 (B4): Output Power Good with Open-Drain Logic
of the Channel 2 Switching Mode Regulator. PGOOD2 is
pulled to ground when the voltage on the VOUT2 pin is
not within ±8% (typical) of the VDDQIN/2 voltage. This
threshold has 15mV of hysteresis.
SYNC/MODE (C5): Mode Select and External
Synchronization Input. Tie this pin to ground to force
continuous synchronous operation at all output loads.
Floating this pin or tying it to INTVCC enables high effi-
ciency Burst Mode operation at light loads. Drive this
pin with a clock to synchronize the LTM4632 switching
frequency. An internal phase-locked loop will force the
bottom power NMOS’s turn on signal to be synchronized
with the rising edge of the clock signal. When this pin is
driven with a clock, forced continuous mode is automati-
cally selected.
INTVCC (C3): Internal 3.3V Regulator Output of the
Switching Mode Regulator Channel. The internal power
drivers and control circuits are powered from this volt-
age. This pin is internally decoupled to GND with a 2.2µF
low ESR ceramic capacitor. No more external decoupling
capacitor needed.
RUN1 (D2), RUN2 (B2): Run Control Input of Each
Switching Mode Regulator Channel. Enables chip opera-
tion by tying RUN above 1.28V. Tying this pin below 1V
shuts down the specific regulator channel. Do not float
this pin.
COMP1 (E5), COMP2 (A5): Current Control Threshold and
Error Amplifier Compensation Point of Each Switching
Mode Regulator Channel. The current comparator’s trip
threshold is linearly proportional to this voltage, whose
normal range is from 0.3V to 1.8V. The device is inter-
nal compensated. Tie COMP pins together in Dual Phase
Single Output VTT Configuration. See the Applications
Information section for details.
FB1 (E4): The Negative Input of the Error Amplifier for
the Channel 1 Switching Mode Regulator. Internally,
this pin is connected to VOUT1 with a 60.4k precision
resistor. Different output voltages can be programmed
with an additional resistor between FB1 and GND pins.
Connect this pin to INTVCC in Dual Phase Single Output
VTT Configuration. See the Applications Information sec-
tion for details.
TRACK/SS1 (E3): Output Tracking and Soft-Start Pin of
the Channel 1 Switching Mode Regulator. It allows the
user to control the rise time of the output voltage. Putting
a voltage below 0.6V on this pin bypasses the internal
reference input to the error amplifier, instead it servos the
FB pin to the TRACK/SS voltage. Above 0.6V, the tracking
function stops and the internal reference resumes control
of the error amplifier. There’s an internal 1.2µA pull-up
current from INTVCC on this pin, so putting a capacitor
here provides a soft-start function.
VTTR (A3): Reference Output. This output is used to sup-
ply the VREF voltage for DDR memory. An on-chip buffer
amplifier outputs a low noise reference voltage equal to
VDDQIN/2. This output is capable of supplying 10mA. VTTR
has internal 0.01µF capacitor. Additional R-C filter can
be used to further reduce the ripple on VTTR. The error
amplifier for channel 2 uses this voltage as its reference
voltage.
VDDQIN (A4): External Reference Input for Channel 2. An
internal resistor divider sets the VTTR pin voltage to be
equal to half the voltage applied to this input. Channel 2
uses the VTTR pin voltage as its error amplifier reference.


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