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AK5522 датащи(PDF) 22 Page - Asahi Kasei Microsystems |
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AK5522 датащи(HTML) 22 Page - Asahi Kasei Microsystems |
22 / 84 page [AK5522] 017002311-E-00 2017/03 - 22 - ■ Power-down, Reset (Parallel Control Mode) (Ta= 40 - +105C; AVDD=3.0 - 3.6V or 4.5 - 5.5V, DVDD=3.0 - 3.6V or 1.7 - 1.98V, unless otherwise specified) Parameter Symbol Min. Typ. Max. Unit Power-down & Reset Timing PDN Accept Pulse Width (Note 19) PDN Reject Pulse Width tPD tRPD 150 - - - - 30 ns ns Note 19. The AK5522 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held “L” for more than 150ns for a certain reset. The AK5522 is not reset by the “L” pulse less than 30ns. ■ Timing Diagram (Parallel Control Mode) Clock Timings (Parallel Control Mode) Figure 15. Clock Timing (External Master Mode) Figure 16. Clock Timing (External Slave Mode) MCLK (I) 1/fMCLK tMCLKH tMCLKL LRCK (I) 1/fs tLRCKH tLRCKL BICK (I) tBICK tBICKH tBICKL VIH min. VIL max. VIL max. VIH min. VIH min. VIL max. dLRCK = tLRCKH fs100 [%] MCLK (I) 1/fMCLK tMCLKH tMCLKL LRCK (O) 1/fs tLRCKH tLRCKL BICK (O) tBICK tBICKH tBICKL 50%DVDD 50%DVDD VIH min. VIL max. dLRCK = tLRCKH fs100 [%] dBICK = tBICKH/tBICK 100 [%] tBICK80 tBICK20 80%DVDD 20%DVDD 80%DVDD 20%DVDD tLRCK80 tLRCK20 |
Аналогичный номер детали - AK5522 |
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Аналогичное описание - AK5522 |
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