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LTM4676A датащи(PDF) 53 Page - Linear Technology

номер детали LTM4676A
подробное описание детали  Dual 13A or Single 26A 關Module Regulator with Digital Power System Management
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производитель  LINER [Linear Technology]
домашняя страница  http://www.linear.com
Logo LINER - Linear Technology

LTM4676A датащи(HTML) 53 Page - Linear Technology

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LTM4676A
53
4676afa
For more information www.linear.com/LTM4676A
applicaTions inForMaTion
The relative phasing of all active channels in a PolyPhase
rail should be optimally phased. The relative phasing of
each rail is 360°/n, where n is the number of phases in
the rail. MFR_PWM_CONFIG[2:0] configures channel
relative phasing with respect to the SYNC pin. Phase
relationship values are indicated with 0° corresponding
to the falling edge of SYNC being coincident with the
turn-on of the top MOSFETs, MTn.
The MFR_PWM_CONFIG command can be altered
via I2C commands, but only when switching action is
disengaged, i.e., the module’s outputs are turned off. The
MFR_PWM_CONFIG command takes on the value stored
in NVM at SVIN power-up, but is overridden according to
aresistorpin-strapappliedbetweentheFSWPHCFGpinand
SGND only if the module is configured to respect resistor
pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 4
highlights available resistor pin-strap and corresponding
MFR_PWM_CONFIG[2:0] settings.
Some combinations of FREQUENCY_SWITCH and
MFR_PWM_CONFIG[2:0] are not available by resistor
pin-strapping the FSWPHCFG pin. All combinations
of supported values for FREQUENCY_SWITCH and
MFR_PWM_CONFIG[2:0] can be configured by NVM
programming—or, I2C transactions, provided switching
action is disengaged, i.e., the module’s outputs are
turned off.
Care must be taken to minimize capacitance on SYNC
to assure that the pull-up resistor versus the capacitor
load has a low enough time constant for the application
to form a “clean” clock. (See “Open-Drain Pins”, later
in this section.)
When an LTM4676A is configured as a sync slave, it is
permissible for external circuitry to drive the SYNC pin
from a current-limited source (less than 10mA), rather
than using a pull-up resistor. Any external circuitry must
not drive high with arbitrarily low impedance at SVIN
power-up,becausetheSYNCoutputcanbelowimpedance
until NVM contents have been downloaded to RAM.
Recommended LTM4676A switching frequencies of
operation for many common VIN-to-VOUT applications
are indicated in Table 7. When the two channels of an
LTM4676A are stepping input voltage(s) down to output
voltages whose recommended switching frequencies in
Table7aresignificantlydifferent,operationatthehigherof
thetworecommendedswitchingfrequenciesispreferable,
butminimumon-timemustbeconsidered.(SeeMinimum
On-Time Considerations section.) For example, consider
an application in which it is desired for an LTM4676A to
step-down 24VIN to 1.5VOUT on Channel 0, and 24VIN
to 3.3VOUT on Channel  1: according to Table  7, the
recommendedswitchingfrequencyis425kHzand750kHz,
respectively. However, the switching frequency setting
of the LTM4676A is common to both channels. Based
on the aforementioned guidance, operation at 750kHz
would be preferred—in order to keep inductor ripple
currents reasonable—however, it is then realized that
the on-time for a 24VIN to 1.5VOUT condition at 750kHz
is 83ns, shy of the 90ns guardband recommendation.
Therefore, for this particular example, the recommended
switching frequency becomes 650kHz.
Table 7. Recommended Switching Frequency for Various
VIN-to-VOUT Step-Down Scenarios
5VIN
8VIN
12VIN
24VIN
0.9VOUT
350kHz
350kHz
350kHz
250kHz
1.0VOUT
350kHz
350kHz
350kHz
250kHz
1.2VOUT
350kHz
350kHz
350kHz
350kHz
1.5VOUT
350kHz
350kHz
425kHz
425kHz
1.8VOUT
425kHz
425kHz
500kHz
500kHz
2.5VOUT
425kHz
500kHz
575kHz
650kHz
3.3VOUT
425kHz
575kHz
650kHz
750kHz
5.0VOUT
N/A
500kHz
750kHz
1MHz
The current drawn by the SVIN pin of the LTM4676A is not
digitized or computed. A value representing the estimated
SVINcurrentislocatedintheMFR_IIN_OFFSETncommand,
and is used in the computations of input current readback
telemetry, namely READ_IIN and and MFR_READ_IINn.
The recommended setting of MFR_IIN_OFFSETn is
found in Table 8. The same value should be used for
MFR_IIN_OFFSET0 and MFR_IIN_OFFSET1 (i.e., Pages
0x00 and 0x01).


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