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TC9455F датащи(PDF) 5 Page - Toshiba Semiconductor |
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TC9455F датащи(HTML) 5 Page - Toshiba Semiconductor |
5 / 14 page TC9455,88F/N 2002-02-05 5 3. AD/DA converter and digital delay circuit The AD/DA converter is a 12-bit successive comparison type. The sampling frequency when the system clock operates at 4 MHz is 32 kHz. The analog signal input from the AD converter is converted to 12-bit digital data. The digital delay circuit compresses the 12-bit signal to 4-bit, writes it to delay RAM, then reads it. The 4-bit data read from delay RAM is de-compressed to 12-bit. The 12-bit data are converted to analog signals by the DA converter and output. The area for delay RAM memory is 4096 words × 4 bits. The echo delay time is 4096 words × (1/32 kHz) = 128 ms. Figure 3 is a block diagram of the echo circuit. Figure 3 Block diagram of echo circuit |
Аналогичный номер детали - TC9455F |
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Аналогичное описание - TC9455F |
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