поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

CXK79M36C162GB-33 датащи(PDF) 6 Page - Sony Corporation

номер детали CXK79M36C162GB-33
подробное описание детали  18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36)
Download  25 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  SONY [Sony Corporation]
домашняя страница  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXK79M36C162GB-33 датащи(HTML) 6 Page - Sony Corporation

Back Button CXK79M36C162GB-33 Datasheet HTML 2Page - Sony Corporation CXK79M36C162GB-33 Datasheet HTML 3Page - Sony Corporation CXK79M36C162GB-33 Datasheet HTML 4Page - Sony Corporation CXK79M36C162GB-33 Datasheet HTML 5Page - Sony Corporation CXK79M36C162GB-33 Datasheet HTML 6Page - Sony Corporation CXK79M36C162GB-33 Datasheet HTML 7Page - Sony Corporation CXK79M36C162GB-33 Datasheet HTML 8Page - Sony Corporation CXK79M36C162GB-33 Datasheet HTML 9Page - Sony Corporation CXK79M36C162GB-33 Datasheet HTML 10Page - Sony Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 25 page
background image
SONY®
ΣRAM
Preliminary
18Mb 1x2Lp, HSTL, rev 1.1
6 / 25
November 8, 2002
CXK79M36C162GB
Burst (Continue) Operations
Because two pieces of data are always transferred during read and write operations, the least significant address bit (A0) of
the internal memory array is not available as an external address pin to these devices. Rather, the address bit is set to “0”
internally prior to the first data transfer and set to “1” internally prior to the second data transfer. Consequently, the two pieces
of data transferred during read and write operations are always read in the same address sequence in which they are written.
Burst operations follow the simple address sequence depicted in the table below:
One (1) Continue operation may be initiated after a Read or Write operation is initiated to burst transfer four (4) distinct piec-
es of data per single external address input. If a second (2nd) Continue operation is initiated, the internal address wraps back
to the initial external (base) address.
Depth Expansion
Depth expansion in these devices is supported via programmable chip enables E2 and E3. The active levels of E2 and E3 are
programmable through the static inputs EP2 and EP3 respectively. When EP2 is tied “high”, E2 functions as an active-high
input. When EP2 is tied “low”, E2 functions as an active-low input. Similarly, when EP3 is tied “high”, E3 functions as an
active-high input. And, when EP3 is tied “low”, E3 functions as an active-low input.
The programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By
programming E2 and E3 of four devices in a binary sequence (00, 01, 10, 11), and by driving E2 and E3 with external address
signals, the four devices can be made to look like one larger device.
When these devices are deselected via chip enable E1, the output clocks continue to toggle. However, when these devices
are deselected via programmable chip enables E2 or E3, the output clocks are forced to a Hi-Z state. See the Clock Truth
Table for further information.
Output Driver Impedance Control
The impedance of the data and clock output drivers in these devices can be controlled via the static input ZQ. When an ex-
ternal impedance matching resistor (RQ) is connected between ZQ and VSS, output driver impedance is set to one-fifth the
value of the resistor, nominally. See the DC Electrical Characteristics section for further information.
Output driver impedance is updated whenever the data output drivers are in an inactive (High-Z) state. See the Clock Truth
Table section for information concerning which commands deactivate the data output drivers.
At power up, 8192 clock cycles followed by any command that deactivates the data output drivers are required to ensure that
the output impedance has reached the desired value.
Note: The impedance of the output drivers will drift somewhat due to changes in temperature and voltage. Consequently,
during operation, the output drivers should be deactivated periodically in order to update the output impedance and ensure
that it remains within specified tolerances.
Power-Up Sequence
For reliability purposes, Sony recommends that power supplies power up in the following sequence: VSS,VDD,VDDQ,VREF,
and Inputs. VDDQ should never exceed VDD. If this power supply sequence cannot be met, a large bypass diode may be re-
quired between VDD and VDDQ. Please contact Sony Memory Application Department for further information.
A1
A1
Sequence Key
1st (Base) Address
0
1
A1
2nd Address
1
0
A1


Аналогичный номер детали - CXK79M36C162GB-33

производительномер деталидатащиподробное описание детали
logo
Sony Corporation
CXK79M36C164GB SONY-CXK79M36C164GB Datasheet
476Kb / 28P
   18Mb 1x1Dp HSTL High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36)
CXK79M36C165GB SONY-CXK79M36C165GB Datasheet
450Kb / 29P
   18Mb 1x1Dp LVCMOS High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36)
More results

Аналогичное описание - CXK79M36C162GB-33

производительномер деталидатащиподробное описание детали
logo
Sony Corporation
CXK79M72C164GB SONY-CXK79M72C164GB Datasheet
476Kb / 28P
   18Mb 1x1Dp HSTL High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36)
CXK79M72C165GB SONY-CXK79M72C165GB Datasheet
450Kb / 29P
   18Mb 1x1Dp LVCMOS High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36)
CXK77P36E160GB SONY-CXK77P36E160GB Datasheet
257Kb / 25P
   16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)
logo
GSI Technology
GS8161E18BT GSI-GS8161E18BT Datasheet
1Mb / 35P
   1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BT-V GSI-GS8161E18BT-V Datasheet
1Mb / 35P
   1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8160E18T GSI-GS8160E18T Datasheet
622Kb / 25P
   1M x 18, 512K x 36 18Mb Sync Burst SRAMs
GS8160V18CT GSI-GS8160V18CT Datasheet
558Kb / 21P
   1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
GS8161V18CD GSI-GS8161V18CD Datasheet
776Kb / 28P
   1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
GS816018C GSI-GS816018C Datasheet
567Kb / 22P
   1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
GS816118C GSI-GS816118C Datasheet
769Kb / 29P
   1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25


датащи скачать

Go To PDF Page


ссылки URL




Конфиденциальность
ALLDATASHEETRU.COM
Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com