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CXK79M36C162GB-33 датащи(PDF) 6 Page - Sony Corporation |
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CXK79M36C162GB-33 датащи(HTML) 6 Page - Sony Corporation |
6 / 25 page SONY® ΣRAM Preliminary 18Mb 1x2Lp, HSTL, rev 1.1 6 / 25 November 8, 2002 CXK79M36C162GB •Burst (Continue) Operations Because two pieces of data are always transferred during read and write operations, the least significant address bit (A0) of the internal memory array is not available as an external address pin to these devices. Rather, the address bit is set to “0” internally prior to the first data transfer and set to “1” internally prior to the second data transfer. Consequently, the two pieces of data transferred during read and write operations are always read in the same address sequence in which they are written. Burst operations follow the simple address sequence depicted in the table below: One (1) Continue operation may be initiated after a Read or Write operation is initiated to burst transfer four (4) distinct piec- es of data per single external address input. If a second (2nd) Continue operation is initiated, the internal address wraps back to the initial external (base) address. •Depth Expansion Depth expansion in these devices is supported via programmable chip enables E2 and E3. The active levels of E2 and E3 are programmable through the static inputs EP2 and EP3 respectively. When EP2 is tied “high”, E2 functions as an active-high input. When EP2 is tied “low”, E2 functions as an active-low input. Similarly, when EP3 is tied “high”, E3 functions as an active-high input. And, when EP3 is tied “low”, E3 functions as an active-low input. The programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming E2 and E3 of four devices in a binary sequence (00, 01, 10, 11), and by driving E2 and E3 with external address signals, the four devices can be made to look like one larger device. When these devices are deselected via chip enable E1, the output clocks continue to toggle. However, when these devices are deselected via programmable chip enables E2 or E3, the output clocks are forced to a Hi-Z state. See the Clock Truth Table for further information. •Output Driver Impedance Control The impedance of the data and clock output drivers in these devices can be controlled via the static input ZQ. When an ex- ternal impedance matching resistor (RQ) is connected between ZQ and VSS, output driver impedance is set to one-fifth the value of the resistor, nominally. See the DC Electrical Characteristics section for further information. Output driver impedance is updated whenever the data output drivers are in an inactive (High-Z) state. See the Clock Truth Table section for information concerning which commands deactivate the data output drivers. At power up, 8192 clock cycles followed by any command that deactivates the data output drivers are required to ensure that the output impedance has reached the desired value. Note: The impedance of the output drivers will drift somewhat due to changes in temperature and voltage. Consequently, during operation, the output drivers should be deactivated periodically in order to update the output impedance and ensure that it remains within specified tolerances. •Power-Up Sequence For reliability purposes, Sony recommends that power supplies power up in the following sequence: VSS,VDD,VDDQ,VREF, and Inputs. VDDQ should never exceed VDD. If this power supply sequence cannot be met, a large bypass diode may be re- quired between VDD and VDDQ. Please contact Sony Memory Application Department for further information. A1 A1 Sequence Key 1st (Base) Address 0 1 A1 2nd Address 1 0 A1 |
Аналогичный номер детали - CXK79M36C162GB-33 |
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Аналогичное описание - CXK79M36C162GB-33 |
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