REV. 0

–6–

AD5425

PIN CONFIGURATION

10

SDIN

56

SYNC

SCLK

47

LDAC

GND

38

AD5425

(Not to Scale)

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Function

DAC Current Output.

DAC Analog Ground. This pin should normally be tied to the analog ground of the system.

3GND

Digital Ground Pin.

4

SCLK

Serial Clock Input. Data is clocked into the input shift register on each falling edge of the serial clock input.

This device can accommodate clock rates of up to 50 MHz.

5SDIN

Serial Data Input. Data is clocked into the 8-bit input register on each falling edge of the serial clock input.

6

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When

SYNC goes

low, it powers on the SCLK and DIN buffers and the input shift register is enabled. Data is transferred on

each falling edge of the following 8 clocks.

7

LDAC

Load DAC Input. Updates the DAC output. The DAC is updated when this signal goes low or alternatively,

if this line is held permanently low, an automatic update mode is selected whereby the DAC is updated

after 8 SCLK falling edges with

SYNC low.

Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.

DAC Reference Voltage Input Terminal.

10

DAC Feedback Resistor Pin. Establishes voltage output for the DAC by connecting to external amplifier output.