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AD5425YRM-REEL датащи(PDF) 11 Page - Analog Devices |
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AD5425YRM-REEL датащи(HTML) 11 Page - Analog Devices |
11 / 20 page REV. 0 AD5425 –11– DAC SECTION The AD5425 is an 8-bit current output DAC consisting of a standard inverting R-2R ladder configuration. A simplified diagram is shown in Figure 2. The feedback resistor RFB has a value of R. The value of R is typically 10 k Ω (minimum 8 kΩ and maximum 12 k Ω). If I OUT1 and IOUT2 are kept at the same potential, a constant current flows in each ladder leg, regardless of digital input code. Therefore, the input resistance presented at VREF is always constant and nominally of value R. The DAC output (IOUT) is code-dependent, producing various resistances and capacitances. External amplifier choice should take into account the variation in impedance generated by the DAC on the amplifiers inverting input node. VREF IOUT2 DAC DATA LATCHES AND DRIVERS 2R S1 2R S2 2R S3 2R S8 2R R R R IOUT1 RFB A R Figure 2. Simplified Ladder Access is provided to the VREF, RFB, IOUT1 and IOUT2 terminals of the DAC, making the device extremely versatile and allowing it to be configured in several different operating modes, for example, to provide a unipolar output, bipolar output, or in single-supply modes of operation in unipolar mode or 4-quadrant multiplication in bipolar mode. Note that a matching switch is used in series with the internal RFB feedback resistor. If users attempt to mea- sure RFB, power must be applied to VDD to achieve continuity. SERIAL INTERFACE The AD5425 has a simple 3-wire interface which is compatible with SPI/QSPI/MICROWIRE and DSP interface standards. Data is written to the device in 8 bit words. This 8-bit word consists of 8 data bits as shown in Figure 3. DB0 (LSB) DB7 (MSB) DATA BITS DB7 DB6 DB5 DB4 DB3 DB2 DB0 DB1 Figure 3. 8-Bit Input Shift Register Contents SYNC is an edge-triggered input that acts as a frame synchroni- zation signal and chip enable. Data can be transferred into the device only while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC falling to SCLK falling edge setup time, t4. After loading eight data bits to the shift register, the SYNC line is brought high. The contents of the DAC register and the output will be updated by bringing LDAC low any time after the 8-bit data transfer is complete as seen in the timing diagram of Figure 1. LDAC may be tied permanently low if required. For another serial transfer to take place, the interface must be enabled by another falling edge of SYNC. Low Power Serial Interface To minimize the power consumption of the device, the interface powers up fully only when the device is being written to, i.e., on the falling edge of SYNC. The SCLK and SDIN input buffers are powered down on the rising edge of SYNC. CIRCUIT OPERATION Unipolar Mode Using a single op amp, this device can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing as shown in Figure 4. When an output amplifier is connected in unipolar mode, the output voltage is given by: V–V OUT REF =× D n 2 where D is the fractional representation of the digital word loaded to the DAC, in this case 0 to 255, and n is the number of bits. Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. This DAC is designed to operate with either negative or positive reference voltages. The VDD power pin is used by only the internal digital logic to drive the DAC switches’ on and off states. This DAC is also designed to accommodate ac reference input signals in the range of –10 V to +10 V. VOUT = 0 TO –VREF SCLK SDIN GND VREF SYNC IOUT2 IOUT1 RFB MICROCONTROLLER AGND AD5425 NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. C1 PHASE COMPENSATION (1pF – 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. R1 R2 A1 VREF VDD VDD C1 Figure 4. Unipolar Operation With a fixed 10 V reference, the circuit shown in Figure 4 will give an unipolar 0 V to –10 V output voltage swing. When VIN is an ac signal, the circuit performs 2-quadrant multiplication. Table I shows the relationship between digital code and the expected output voltage for unipolar operation. Table I. Unipolar Code Table Digital Input Analog Output (V) 1111 1111 –VREF (255/256) 1000 0000 –VREF (128/256) = –VREF/2 0000 0001 –VREF (1/256) 0000 0000 –VREF (0/256) = 0 |
Аналогичный номер детали - AD5425YRM-REEL |
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Аналогичное описание - AD5425YRM-REEL |
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