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AD7680 датащи(PDF) 9 Page - Analog Devices |
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AD7680 датащи(HTML) 9 Page - Analog Devices |
9 / 11 page –9– REV. PrE AD7680 PRELIMINARY TECHNICAL DATA Power-Down Mode This mode is intended for use in applications where slower throughput rates are required; either the ADC is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and then the ADC is powered down for a relatively long duration between these bursts of several conversions. When the AD7680 is in power down, all analog circuitry is powered down. To enter Power-Down, the conversion process must be interrupted by bringing CS high anywhere after the second falling edge of SCLK and before the tenth falling edge of SCLK as shown in Figure 8. Once CS has been brought high in this window of SCLKs, then the part will enter power down and the conversion that was intiated by the falling edge of CS will be terminated and SDATA will go back into tri-state. If CS is brought high before the second SCLK falling edge, then the part will remain in Normal Mode and will not power-down. This will avoid accidental powerdown due to glitches on the CS line. In order to exit this mode of operation and power the AD7680 up again, a dummy conversion is performed. On the falling edge of CS the device will begin to power up, and will continue to power up as long as CS is held low until after the falling edge of the tenth SCLK. The device will be fully powered up once at least 16 SCLKs ( or ap- proximately 6us) have elapsed and valid data will result from the next conversion as shown in figure 9. If CS is brought high before the tenth falling edge of SCLK, re- gardless of SCLK frequency, then the AD7680 will go back into power down again. This avoids accidental power up due to glitches on the CS line or an inadvertent burst of 8 SCLK cycles while CS is low. So although the device may begin to power up on the falling edge of CS, it will power down again on the rising edge of CS as long as it occurs before the tenth SCLK falling edge. Figure 7. Normal Mode Operation SCLK 4 LEADING ZEROS + CONVERSION RESULT CS SDATA 1 20 10 SCLK THREE-STATE CS SDATA 1 20 10 2 Figure 8. Entering Power Down Mode Normal Mode This mode is intended for fastest throughput rate perfor- mance as the user does not have to worry about any power-up times with the AD7680 remaining fully-powered all the time. Figure 7 shows the general diagram of the operation of the AD7680 in this mode. The conversion is iniated on the falling edge of CS as described in the Serial Interface section. To ensure the part remains fully powered up at all times CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the 10th SCLK falling edge but before the 20th SCLK falling edge the part will remain powered up but the conversion will be terminated and SDATA will go back into tri-state. At least twenty serial clock cycles are required to complete the conversion and access the com- plete conversion result. A total of twenty-four SCLK cycles will access four trailing zeros in addtion. CS may idle high until the next conversion or may idle low until CS returns high sometime prior to the next conversion, (effectively idling CS low). Once a data transfer is complete (SDATA has returned to tri-state), another conversion can be initiated after the quiet time, tquiet, has elapsed by bringing CS low again. Figure 9. Exiting Power Down Mode SCLK CS SDATA INVALID DATA VALID DATA 1 10 20 20 1 THE PART BEGINS TO POWER UP tpower up THE PART IS FULLY POWERED UP WITH V IN FULLY ACQUIRED |
Аналогичный номер детали - AD7680 |
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Аналогичное описание - AD7680 |
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