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CD4070B датащит (Datasheet) 1 Page - Silicon Supplies

№ деталь CD4070B
подробность  CMOS High Voltage Logic
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производитель  SS [Silicon Supplies]
домашняя страница  https://siliconsupplies.com/
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 CMOS High Voltage Logic – CD4070B
 
Quadruple Exclusive-OR Gate Logic IC in bare die form
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Die Size (Unsawn)
1900 x 1850
75 x 73
µm
mils
Minimum Bond Pad Size
106 x 106
4.17 x 4.17
µm
mils
Die Thickness
350 (±20)
13.78 (±0.79)
µm
mils
Top Metal Composition
Al 1%Si 1.1µm
Back Metal Composition
N/A – Bare Si
High Input Voltage up to 20V
Noise immunity greater than 50%
All outputs buffered
Drives x2 Low-Power TTL loads or x1 LSTTL load
Symmetrical Sink & Source Currents
Direct drop-in replacement for obsolete
components in long term programs.  
Rev 1.0
15/03/18
Description
Features:
The CD4070B Quad Exclusive OR Gate is fabricated
using a 3µm 15CMOS process. This device consists of
four independent Exclusive OR gates and performs the
Boolean functions Y = A ⊕ B = AB + AB in positive
logic. The device has equal source and sink current
capabilities and conforms to standard B series output
drive. Inputs are protected against ESD and voltage
transients by diode clamps to VDD and VSS.
Ordering Information
Die Dimensions in µm (mils)
1900 (75)
The following part suffixes apply:
No suffix - MIL-STD-883 /2010B Visual Inspection
“H” - MIL-STD-883 /2010B Visual Inspection
+ MIL-PRF-38534 Class H LAT
“K” - MIL-STD-883 /2010A Visual Inspection (Space)
+ MIL-PRF-38534 Class K LAT
LAT = Lot Acceptance Test.
For further information on LAT process flows see below.
www.siliconsupplies.com\quality\bare-die-lot-qualification
Supply Formats:
Mechanical Specification
Default – Die in Waffle Pack (100 per tray capacity)
Sawn Wafer on Tape – On request
Unsawn Wafer – On request
Die Thickness <> 350µm(14 Mils) – On request
Assembled into Ceramic Package – On request
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