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WS7808QM датащит (Datasheet) 10 Page - Will Semiconductor Ltd.

№ деталь WS7808QM
подробность  0.1GHz–3GHz SP8TDiversityAntenna Switch with MIPI RFFE Interface
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производитель  WILLSEMI [Will Semiconductor Ltd.]
домашняя страница  http://www.willsemi.com/index.php?siteid=2
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WS7808QM
Will Semiconductor Ltd.
Mar, 2018_V1.4
Trigger_Mask_2
Bit[5]:
If this bit is set, trigger 2 is disabled. When all
triggers are disabled, if writing to a register
that is associated with trigger 2, the data
goes directly to the destination register.
0
Trigger_Mask_1
Bit[4]:
If this bit is set, trigger 1 is disabled. When all
triggers are disabled, if writing to a register
that is associated with trigger 1, the data
goes directly to the destination register.
0
Trigger_Mask_0
Bit[3]:
If this bit is set, trigger 0 is disabled. When all
triggers are disabled, if writing to a register
that is associated with trigger 0, the data
goes directly to the destination register.
0
Trigger_2
Bit[2]:
If this bit is set, data is loaded into the trigger
2 registers.
0
Trigger_1
Bit[1]:
If this bit is set, data is loaded into the trigger
1 registers.
0
Trigger_0
Bit[0]:
If this bit is set, data is loaded into the trigger
0 registers.
0
PRODUCT_ID
001D
PRODUCT_ID
Bits[7:0]:
This is a read-only register. However, during
the programming of the Unique Slave
Identifier (USID), a write command sequence
is performed on this register but the value is
not changed.
00001000
MANUFAC-
TURER_ID
001E
MANUFACTURER_ID
Bits[7:0]:
Read-only register
10111100
MAN_USID
001F
Reserved
Bits[7:6]:
Reserved
00
MANUFACTURER_ID
Bits[5:4]:
Read-only register
11
USID
Bits[3:0]:
Programmable USID. A write to these bits
programs the USID.
1010
Note 3: Unlike the complete independence between triggers 0, 1, and 2, and also between the associated trigger masks 0, 1, and 2,
respectively, as described in the MIPI RFFE Specificationthis device uses additional interactions between the provided trigger functions.
The delayed application of updated data to all triggerable registers in this device may be accomplished using any of the three triggers (0,
1, or 2), provided that the particular triggerableused is not currently masked off. If multiple triggers are enabled, any or all of those are
sufficient to cause the data to be transferred from shadow registers to destination registers forall triggerable registers in the device.
It is also necessary to disable all three triggers (i.e., set all three trigger masks) to ensure that data written to any triggerable register will
immediately be written to the destinationregister at the conclusion of the RFFE command sequence where the data is written.




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