Single-Conversion DVB-H Tuner

14

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BIT NAME

BIT LOCATION

(0 = LSB)

FUNCTION

X

7

Reserved. Set to 0 for normal operation.

DC_DAC8

6

Most significant bit of the DC offset correction DAC.

DC_MO[1:0]

5, 4

Controls the DC offset correction mode of operation:

00 = Offset correction disabled.

01, 10 = I/Q channel DC correction DACs are programmed direct from the DC_DAC[8:0]

bits for manual offset correction.

11 = Normal operation.

DC_SP[1:0]

3, 2

Controls the DC offset correction speed (highpass corner frequency):

00 = Offset correction off, hold DAC values.

01 = Select correction speed 1 (slowest correction speed, ~20Hz highpass corner).

10 = Select correction speed 2.

11 = Select correction speed 3 (fastest correction speed, ~500Hz highpass corner).

DC_TH[1:0]

1, 0

Control the DC offset correction accuracy thresholds:

00 = Not recommended.

01 = Keep typical DC offset to within ±100mV.

10 = Keep typical DC offset to within ±200mV.

11 = Keep typical DC offset to within ±400mV.

Table 13. DC Offset Control Register (Address: 0x0B)

BIT NAME

BIT LOCATION

(0 = LSB)

FUNCTION

DC_DAC[7:0]

7–0

Programs the I/Q DC offset DAC for manual DC offset correction. Note the MSB,

DC_DAC8, is located in the DC Offset Control register.

Table 14. DC Offset DAC Register (Address: 0x0C)

BIT NAME

BIT LOCATION

(0 = LSB)

FUNCTION

X

7–4

Reserved. Set to 0000 for normal operation.

TFA[3:0]

3–0

Programs which ROM table address that data is to be read from (see Table 21):

0001 = Tracking filter notch coefficients for 783MHz and 725MHz.

0010 = Balun coefficients for 470MHz and 780MHz.

0011 = Baseband filter bandwidth settings for 7MHz and 8MHz channels.

All other codes = Reserved.

Table 15. ROM Table Address Register (Address: 0x0D)

BIT NAME

BIT LOCATION

(0 = LSB)

FUNCTION

X

7–0

Reserved. Set to 0x00 for normal operation.

Table 16. Reserved Register (Address: 0x0E)