поискавой системы для электроныых деталей |
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GD25B16C датащи(PDF) 16 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25B16C датащи(HTML) 16 Page - GigaDevice Semiconductor (Beijing) Inc. |
16 / 53 page 3.3V Uniform Sector Dual and Quad Serial Flash GD25B16C 16 7.1. Write Enable (WREN) (06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR) and Erase/Program Security Registers command. The Write Enable (WREN) command sequence: CS# goes low sending the Write Enable command CS# goes high. Figure 1. Write Enable Sequence Diagram 7.2. Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes low Sending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Power- up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase, Erase/Program Security Registers and Reset commands. Figure 2. Write Disable Sequence Diagram 7.3. Read Status Register (RDSR) (05H or 35H) The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible to r ead the Status Register continuously. For command code “05H”, the SO will output Status Register bits S7~S0. The command code “35H”, the SO will output Status Register bits S15~S8. Command 0 1 2 3 4 5 6 7 06H CS# SCLK SI SO High-Z Command 0 1 2 3 4 5 6 7 04H CS# SCLK SI SO High-Z |
Аналогичный номер детали - GD25B16C |
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Аналогичное описание - GD25B16C |
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