RTQ2536-QA

3

DSQ2536-QA-01 September 2018

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Copyright 2018 Richtek Technology Corporation. All rights reserved.

is a registered trademark of Richtek Technology Corporation.

Functional Block Diagram

+

-

OCP

+

-

OCP

+

-

VDDQSNS

VIN

SENSE

PGND

VCNTL

S5

GND

REFOUT

VOUT

+

-

EN_VTT

UVLO

OTP

S3

Operation

The RTQ2536-QA is a linear sink/source DDR termination

regulator with current capability up to 2A. The RTQ2536-

QA builds in a high-side N-MOSFET which provides current

sourcing and a low-side N-MOSFET which provides current

sinking. All the control circuits are supplied by the power

VCNTL. In normal operation, the error amplifier OP adjusts

the gate driving voltage of the power MOSFET to achieve

SENSE voltage well tracking the VDDQSNS/2 voltage.

Both the source and sink currents are detected by the

internal sensing resistor, and the OCP function will work

to limit the current to a designed value when overload

happens. Furthermore, the current will be folded back to

be one half if VOUT is out of the power good window.

Buffer

This function provides REFOUT output equal to

VDDQSNS/2 with 10mA source/sink current capability.

Control Logic

This block includes VCNTL UVLO, VDDQSNS UVLO and

Enable/Disable functions, and provides logic control to

the whole chip.

Thermal Protection

Both the high-side and low-side power MOSFETs will be

turned off when the junction temperature is higher than

typically 160

°C, and be released to normal operation when

junction temperature falls below 135

°C typically.

Power State Control

simple control of the power state. Table 1 describes S3/

S5 terminal logic state and corresponding state of

REFOUT/VOUT outputs. VOUT is turn-off and discharged

to GND in state S3. When both S5 and S3 pins are LOW,

the power state is set to S4/S5. In S4/S5 state, all the

Table 1. S3 and S5 Control Table

STATE

S3

S5

REFOUT

VOUT

S0

HI

HI

ON

ON

S3

LO

HI

ON

OFF (Discharge)

S4/S5

LO

LO

OFF (Discharge)

OFF (Discharge)