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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CAT24FC32AWTE13 датащи(PDF) 8 Page - Catalyst Semiconductor |
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CAT24FC32AWTE13 датащи(HTML) 8 Page - Catalyst Semiconductor |
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8 / 12 page  CAT24FC32A 8 Doc. No. 1048, Rev. F Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The SDA line remains stable LOW during the HIGH period of the acknowledge related clock pulse (Figure 8). The CAT24FC32A responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. The CAT24FC32A does not generate acknowledge if an internal write cycle is in progress. When the CAT24FC32A begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24FC32A will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The master must then issue a stop condition to return the CAT24FC32A to the standby power mode and place the device in a known state. Figure 8. Acknowledge Timing WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/ W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends two 8-bit address words that are to be written into the address pointers of the CAT24FC32A. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT24FC32A acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to nonvolatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. Page Write The CAT24FC32A writes up to 32 bytes of data, in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 31 additional bytes. After each byte has ACKNOWLEDGE 1 START SCL FROM MASTER 89 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER Figure 9. Byte Write Timing A15—A 8 SLAVE ADDRESS S A C K A C K DATA A C K S T O P P BUS ACTIVITY: MASTER SDA LINE S T A R T A7—A 0 BYTE ADDRESS A C K X X XX X = Don't care bit |
Аналогичный номер детали - CAT24FC32AWTE13 |
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Аналогичное описание - CAT24FC32AWTE13 |
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