DRAM MODULE

KMM5362203C2W/C2WG

Rev. 0.0 (Nov. 1997)

- 7 -

NOTES

An initial pause of 200us is required after power-up followed

by any 8 RAS-only or CAS-before-RAS refresh cycles before

proper device operation is achieved.

timing of input signals. Transition times are measured

for all inputs.

Measured with a load equivalent to 2 TTL loads and 100pF.

Operation within the

can be met.

If

access time is controlled exclusively by

Assumes that

This parameter defines the time at which the output achieves

the

data

sheet

as

electrical

characteristic s

only.

If

data out pin will remain high impedance for the duration of

the cycle.

Either

These parameter are referenced to the CAS leading edge in

early write cycles.

Operation within the

can be met.

access time is controlled by

In order to hold the address latched by the first CAS going

low, the parameter

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

Parameter

Symbol

-5

-6

Unit

Note

Min

Max

Min

Max

Fast page mode cycle time

35

40

ns

CAS precharge time(Fast page cycle)

10

10

ns

RAS pulse width(Fast page cycle)

50

200K

60

200K

ns

W to RAS precharge time(C-B-R refresh)

10

10

ns

W to RAS hold time(C-B-R refresh)

10

10

ns

Hold time CAS low to CAS

20

5

ns

11

11.