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CDCDB2000 датащит (Datasheet) 5 Page - Texas Instruments

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№ деталь CDCDB2000
подробность  CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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5
CDCDB2000
www.ti.com
SNAS787 – NOVEMBER 2019
Product Folder Links: CDCDB2000
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Copyright © 2019, Texas Instruments Incorporated
Pin Functions (continued)
PIN
I/O TYPE
DESCRIPTION
NAME
NO.
OE6#
CLK
L10
I, PD
Output enable for channel 6 and Side-Band Interface clock multi-function pin with
internal 120-kΩ pulldown. Typically connected to GPIO of microcontroller. If both
modes are unused, the pin can be left no connect.
When pin E2 = LOW, OE6# mode. Output Enable for channel 6, active low.
LOW: enable output channel 6.
HIGH: disable output channel 6.
When pin E2 = HIGH, CLK mode. Side-Band interface clock pin.
OE7#
K11
I, PD
Output Enable for channel 7 with internal 120-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 7.
HIGH: disable output channel 7.
OE8#
H11
I, PD
Output Enable for channel 8, with internal 120-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 8.
HIGH: disable output channel 8.
OE9#
E12
I, PD
Output Enable for channel 9, with internal 120-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 9.
HIGH: disable output channel 9.
OE10#
SHFT_LD#
E11
I, PD
Output enable for channel 10 and Side-Band Interface load shift registers multi-
function pin with internal 120-kΩ pulldown. Typically connected to GPIO of
microcontroller. If both modes are unused, the pin can be left no connect.
When pin E2 = LOW, OE10# mode. Output Enable for channel 10, active low.
LOW: enable output channel 10.
HIGH: disable output channel 10.
When pin E2 = HIGH, SHFT_LD# mode. Side-Band Interface load shift registers
pin.
LOW: disable Side-Band Interface shift register.
HIGH: enable Side-Band Interface shift register.
A falling edge transfers the Side-Band shift register contents to the output register.
OE11#
C11
I, PD
Output Enable for channel 11 with internal 120-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 11.
HIGH: disable output channel 11.
OE12#
B10
I, PD
Output Enable for channel 12 with internal 120-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 12.
HIGH: disable output channel 12.
SBEN
E2
I, S, PD
Side-Band Interface enable input with internal 120-kΩ pulldown. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
This pin disables the Output Enable (OE#) pins when asserted.
LOW: OE# pins and SMBus enable bits control outputs, Side-Band interface
disabled.
HIGH: Side-Band Interface controls outputs, OE# pins and SMBus enable bits are
disabled.
SMBUS AND SMBUS ADDRESS
SADR0
B4
I, S, PU /
PD
SMBus address strap bit[0]. This is a 3-level input that is decoded in conjunction
with pin B8 to set SMBus address. It has internal 120-kΩ pullup / pulldown network
biasing to VDD/2 when no connect.
For a high-level input configuration, the pin should be pulled up to 3.3-V VDD
through an external pullup resistor from 1k to 5k with 5% tolerance.
For a low-level input configuration input, the pin should be pulled down to ground
through an external pulldown resistor from 1k to 5k with 5% tolerance.
For a mid-level input configuration, the pin should be left floating and not
connected to VDD or ground.




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