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CDCDB2000 датащит (Datasheet) 6 Page - Texas Instruments

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№ деталь CDCDB2000
подробность  CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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6
CDCDB2000
SNAS787 – NOVEMBER 2019
www.ti.com
Product Folder Links: CDCDB2000
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Copyright © 2019, Texas Instruments Incorporated
Pin Functions (continued)
PIN
I/O TYPE
DESCRIPTION
NAME
NO.
SADR1
B8
I, S, PU /
PD
SMBus address strap bit[1]. This is a 3-level input that is decoded in conjunction
with pin B4 to set SMBus address. It has internal 120-kΩ pullup / pulldown network
biasing to VDD/2 when no connect.
For a high-level input configuration, the pin should be pulled up to 3.3-V VDD
through an external pullup resistor from 1k to 5k with 5% tolerance.
For a low-level input configuration, the pin should be pulled down to ground
through an external pulldown resistor from 1k to 5k with 5% tolerance.
For a mid-level input configuration, the pin should be left floating and not
connected to VDD or ground.
SMBCLK
L5
I
Clock pin of SMBus interface. Typically pulled up to 3.3-V VDD using external
pullup resistor. The recommended pullup resistor value is > 8.5k.
SMBDAT
L4
I / O
Data pin of SMBus interface. Typically pulled up to 3.3-V VDD using external
pullup resistor. The recommended pullup resistor value is > 8.5k.
SUPPLY VOLTAGE AND GROUND
GND
DAP
G
Ground. Connect ground pad to system ground.
VDD
B2, B6, B11, L2,
L11
P
Power supply input for LP-HCSL clock output channels. Connect to 3.3-V power
supply rail with decoupling capacitor to GND. Place a 0.1-µF capacitor close to
each supply pin between power supply and ground.
VDD_A
H2
P
Power supply input for differential input clock. Connect to 3.3-V power supply rail
with decoupling capacitor to GND. Place a 0.1-µF capacitor close to pin.
NO CONNECT
NC
B3, B5, B7, B9,
C2, D2, D11, F2,
F11, G2, G11, J2,
J11, K2, L3, L6,
L7, L9,
Do not connect to GND or VDD.
The “#” symbol at the end of a pin name indicates that the active state occurs when the signal is at a low voltage
level. When “#” is not present, the signal is active high.
The definitions below define the I/O type for each pin.
I = Input
O = Output
I / O = Input / Output
PU / PD = Internal 120-kΩ Pullup / Pulldown network biasing to VDD/2
PD = Internal 120-kΩ Pulldown
S = Hardware Configuration Pin
P = Power Supply
G = Ground




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