поискавой системы для электроныых деталей
Selected language     Russian  ▼
название детали
         подробно


CDCDB2000 датащит (Datasheet) 9 Page - Texas Instruments

Click here to check the latest version.
№ деталь CDCDB2000
подробность  CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5
скачать  33 Pages
Scroll/Zoom Zoom In 100% Zoom Out
производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
Logo 

 9 page
background image
9
CDCDB2000
www.ti.com
SNAS787 – NOVEMBER 2019
Product Folder Links: CDCDB2000
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Electrical Characteristics (continued)
VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(6)
Measured from rising edge of any CKx output to any other CKx output.
tSKEW
Skew between outputs
(6)50
ps
JCKx_PCIE
Additive jitter
DB2000QL filter
0.08
ps, rms
Additive jitter for PCIe5
PCIe5.0 filter
0.03
ps, rms
Additive jitter for PCIe4
PLL BW = 2 - 5 MHz; CDR =
10 MHz
Input clock
slew rate
≥ 1.8 V/ns
0.08
ps, rms
Additive jitter for PCIe3
Input clock
slew rate
≥ 0.6 V/ns
0.15
ps, rms
JCKx_PCIE
Additive jitter for PCIe2
PCIe2 filter
0.2
ps, rms
JCKx_PCIE
Additive jitter for PCIe1
PCIe1 filter
5
ps, rms
JCKx
Additive jitter
fIN = 100 MHz; slew rate ≥ 3 V/ns; 12 kHz
to 20 MHz integration bandwidth.
155
fs, rms
SMBUS INTERFACE, SIDE-BAND INTERFACE, OEx#, CKPWRGD_PD#, SBEN
VIH
High-level input voltage
2.0
V
VIL
Low-level input voltage
0.8
IIL
Input leakage current
With internal pull up/pull-down
GND < VIN
< VDD
–30
30
uA
Without internal pull up/pull-
down
–5
5
CIN
Input capacitance
4.5
pF
COUT
Output capacitance
4.5
pF
3-LEVEL DIGITAL INTERFACE (SA_0, SA_1)
VIHT
High-level input voltage
2.4
V
VIMT
Mid level input voltage
1.3
VDD/2
1.8
VILT
Low-level input voltage
0.9
IINT
Input high current
VIN = VDD, VIN = GND
-10
10
uA
ILeak
Input leakage current
With internal pull up/pull-down
GND < VIN
< VDD
–30
30
6.6 Timing Requirements
VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise
noted)
MIN
NOM
MAX
UNIT
SMBUS-COMPATIBLE INTERFACE TIMING
fSMB
SMBus operating frequency
10
100
kHz
tBUF
Bus free time between STOP and
START
4.7
µs
tHD_STA
START condition hold time
4
tSU_STA
START condition setup time
4.7
tSU_STO
STOP condition setup time
4
tHD_DAT
SMBDAT hold time
300
ns
tSU_DAT
SMBDAT setup time
250
tTIMEOUT
Detect SMBCLK low timeout
25
35
ms
tLOW
SMBCLK low period
4.7
µs
tHIGH
SMBCLK high period
4
50
tLOW_SL
Cumulative clock low extend time
25
ms




Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33 


датащит скачать




ссылки URL

Вашему бизинису помогли Аллдатащит?  [ DONATE ]  

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность    |   закладка   |   обмен ссыками   |   поиск по производителю
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl