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CDCDB2000 датащит (Datasheet) 14 Page - Texas Instruments

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№ деталь CDCDB2000
подробность  CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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 14 page
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14
CDCDB2000
SNAS787 – NOVEMBER 2019
www.ti.com
Product Folder Links: CDCDB2000
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Copyright © 2019, Texas Instruments Incorporated
Feature Description (continued)
7.3.2.1 SMBus Address Assignment
The SMBus address is assigned by configuration of two pins (SADR1 and SADR0) that each support three
levels. This configuration allows the CDCDB2000 to assume 9 different SMBus addresses.
The SMBus address pins are sampled PWRGD is set to 1. See Table 1 for address pin configuration. The
address cannot be changed until the PWRGD state is cleared by powering down the device.
Table 1. SMBus Address Assignment
SADR1
SADR0
SMBUS ADDRESS
L
L
0xD8
L
M
0xDA
L
H
0xDE
M
L
0xC2
M
M
0xC4
M
H
0xC6
H
L
0xCA
H
M
0xCC
H
H
0xCE
7.3.3 Side-Band Interface
The Side-Band Interface(SBI) is a basic 3-wire interface that consists of the DATA, CLK and SHFT_LD# pins.
The SBI is used to shift data into a 20-bit long shift register. When the SHFT_LD# pin is high, the rising edge of
CLK can shift DATA into the shift register. After shifting data, the falling edge of SHFT_LD# clocks the shift
register contents to the SBI output register.
While SBI is enabled by the SBEN pin, OE[7:9, 11, 12]# pins are disabled and DATA, CLK and SHFT_LD# are
enabled on the OE5#, OE6# and OE10# pins, respectively.
When power has been applied, and SBEN = 1, the SBI is active regardless of the CKPWRGD_PD# pin state.
This characteristic allows loading the shift register and transferring the contents to the SBI output register before
the first assertion of the CKPWRGD_PD# pin.
7.4 Device Functional Modes
7.4.1 CKPWRGD_PD# Function
The CKPWRGD_PD# pin is used to set 2 state variables inside of the device: PWRGD, and PD#. The PWRGD
and PD# variables control which functions of the device are active at any time, as well as the state of the input
and output pins.
The PWRGD and PD# states are multiplexed on the CKPWRGD_PD# pin. CKPWRGD_PD# must remain below
VOL and not exceed VDD_A + 0.3 V until VDD, VDD_A, and CLKIN are present and within the recommended
operating conditions.
The first rising edge of the CKPWRGD_PD# pin sets PWRGD = 1. After PWRGD is set to 1, the
CKPWRGD_PD# pin is used to assert PD# mode only. PWRGD variable will only be cleared to 0 with the
removal of VDD and VDD_A.




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