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DLPC900_V01 датащит (Datasheet) 33 Page - Texas Instruments

№ деталь DLPC900_V01
подробность  DLPC900 Digital Controller for Advanced Light Control
скачать  83 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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 33 page
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33
DLPC900
www.ti.com
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
Product Folder Links: DLPC900
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
(1)
Ports 1 and 2 are both 30-bit buses, but only 24-bits are used.
(2)
For frequencies (ƒclock) less than 175 MHz, use the following formula to obtain the jitter: Max clock jitter = ± [(1 / ƒclock) – 5414 ps].
6.11 Port 1 and 2 Input Pixel Interface Timing Requirements
MIN
MAX
UNIT
ƒclock
Clock frequency, P_CLK1, P_CLK2, P_CLK3 (24-bit bus (1))
12
175
MHz
ƒclock
Clock frequency, P_CLK1, P_CLK2, P_CLK3 (48-bit bus (1))
See Two Pixels Per Clock (48-Bit Bus) Timing Requirements.
12
141
MHz
tc
Cycle time, P_CLK1, P_CLK2, P_CLK3
5.714
83.33
ns
tw(H)
Pulse duration, high
50% to 50% reference points (signal)
2.3
ns
tw(L)
Pulse duration, low
50% to 50% reference points (signal)
2.3
ns
tjp
Clock period jitter P_CLK1, P_CLK2, P_CLK3
(that is, the deviation in period from ideal
period)
Max fclock
See (2)
ps
tt
Transition time, tt = tf / tr , P_CLK1, P_CLK2,
P_CLK3
20% to 80% reference points (signal)
0.6
2.0
ns
tt
Transition time, tt = tf / tr, P1_A(9:0),
P1_B(9:0) , P1_C(9:0), P1_HSYNC,
P1_VSYNC, P1_DATEN
20% to 80% reference points (signal)
0.6
3.0
ns
tt
Transition time, tt = tf / tr
20% to 80% reference points (signal)
0.6
3.0
ns
tsu
Setup time, P1_A(9:0), valid before P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
th
Hold time, P1_A(9:0), valid after P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
tsu
Setup time, P1_B(9:0), valid before P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
th
Hold time, P1_B(9:0), valid after P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
tsu
Setup time, P1_C(9:0), valid before P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
th
Hold time, P1_C(9:0), valid after P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
tsu
Setup time, P1_VSYNC, valid before P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
th
Hold time, P1_VSYNC, valid after P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
tsu
Setup time, P1_HSYNC, valid before P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
th
Hold time, P1_HSYNC, valid after P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
tsu
Setup time, P2_A(9:0), valid before P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
th
Hold time, P2_A(9:0), valid after P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
tsu
Setup time, P2_B(9:0), valid before P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
th
Hold time, P2_B(9:0), valid after P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
tsu
Setup time, P2_C(9:0), valid before P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
th
Hold time, P2_C(9:0), valid after P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
tsu
Setup time, P2_VSYNC, valid before P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
th
Hold time, P2_VSYNC, valid after P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
tsu
Setup time, P2_HSYNC, valid before P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
th
Hold time, P2_HSYNC, valid after P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
tsu
Setup time, P_DATEN1, valid before P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
th
Hold time, P_DATEN1, valid after P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
tsu
Setup time, P_DATEN2, valid before P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
th
Hold time, P_DATEN2, valid after P_CLK1, P_CLK2, or P_CLK3.
0.8
ns
tw(A)
VSYNC active pulse duration
1
Video line
tw(A)
HSYNC active pulse duration
16
Pixel
clocks




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