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DLPC900_V01 датащит (Datasheet) 56 Page - Texas Instruments

№ деталь DLPC900_V01
подробность  DLPC900 Digital Controller for Advanced Light Control
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DLPC900
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
www.ti.com
Product Folder Links: DLPC900
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Copyright © 2014–2019, Texas Instruments Incorporated
8.2.1.2.1.3
DLPC900 System Output Interfaces
DLPC900 system output interfaces include the illumination interface as well as the trigger and sync interface.
8.2.1.2.1.3.1
Illumination Interface
An illumination interface is provided that supports up to a three (3) channel LED driver. The illumination interface
provides signals that support: LED driver enable, LED enable, LED enable select, and PWM signals to control
the LED current.
Table 9. Active Signals - Illumination Interface
SIGNAL NAME
DESCRIPTION
HEARTBEAT
Signal toggles continuously to indicate system is running fine.
FAULT_STATUS
Signal toggles or held high indicating system faults
RED_LED_EN
Red LED enable
GRN_LED_EN
Green LED enable
BLU_LED_EN
Blue LED enable
RED_LED_PWM
Red LED PWM signal used to control the LED current
GRN_LED_PWM
Green LED PWM signal used to control the LED current
BLU_LED_PWM
Blue LED PWM signal used to control the LED current
8.2.1.2.1.3.2
Trigger and Sync Interface
The DLPC900 outputs a trigger signal for synchronizing displayed patterns with a camera, sensor, or other
peripherals. The sync output supporting signals are: horizontal sync, vertical sync, two input triggers, and two
output triggers. Depending on the application, these signals control how the pattern is displayed.
Table 10. Active Signals - Trigger and Sync Interface
SIGNAL NAME
DESCRIPTION
P1_HSYNC
Horizontal Sync
P1_VSYNC
Vertical Sync
TRIG_IN_1
Depending on the mode, advances the pattern display.
TRIG_IN_2
Depending on the mode, starts or stops the pattern display.
TRIG_OUT_1
Active high during pattern exposure
TRIG_OUT_2
Active high pulse to indicate first pattern display
8.2.1.2.1.4
DLPC900 System Support Interfaces
8.2.1.2.1.4.1
Reference Clock and PLL
The DLPC900 controller requires a 20-MHz 3.3-V external input from an oscillator. This signal serves as the
DLPC900 chipset reference clock from which the majority of the interfaces derive their timing. This includes DMD
interfaces and serial interfaces.
Refer to PCB Layout Guidelines for Internal Controller PLL Power on PLL guidelines.




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