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DLPC900 датащи(PDF) 7 Page - Texas Instruments |
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DLPC900 датащи(HTML) 7 Page - Texas Instruments |
7 / 83 page 7 DLPC900 www.ti.com DLPS037D – OCTOBER 2014 – REVISED MARCH 2019 Product Folder Links: DLPC900 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated (1) Refer to I/O Type and Subscript Definition (Table 1). (2) Refer to the Typical Single Controller Chipset and the Typical Two Controller Chipset for a description between a one controller and a two controller configuration. DMD Control Pin Functions PIN I/O POWER I/O TYPE (1) CLK SYSTEM DESCRIPTION (2) NAME NUMBER DADOEZ AE7 VDD33 O5 Async DMD output-enable (active low). This signal does not apply to the slave controller in a two-controller system configuration. On the slave controller, this pin is reserved and should be left unconnected. DADADDR_3 DADADDR_2 DADADDR_1 DADADDR_0 AD6 AE5 AF4 AB8 VDD33 O5 Async DMD address. This signal does not apply to the slave controller in a two-controller system configuration. On the slave controller, this pin is reserved and should be left unconnected. DADMODE_1 DADMODE_0 AD7 AE6 VDD33 O5 Async DMD mode. This signal does not apply to the slave controller in a two-controller system configuration. On the slave controller, this pin is reserved and should be left unconnected. DADSEL_1 DADSEL_0 AE4 AC7 VDD33 O5 Async DMD select. This signal does not apply to the slave controller in a two-controller system configuration. On the slave controller, this pin is reserved and should be left unconnected. DADSTRB AF5 VDD33 O5 Async DMD strobe. This signal does not apply to the slave controller in a two-controller system configuration. On the slave controller, this pin is reserved and should be left unconnected. DAD_INTZ AC8 VDD33 I4 H Async DMD interrupt (active low). Requires an external 1-kΩ pullup resistor. |
Аналогичный номер детали - DLPC900_V01 |
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Аналогичное описание - DLPC900_V01 |
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