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DLPC900_V01 датащит (Datasheet) 72 Page - Texas Instruments

№ деталь DLPC900_V01
подробность  DLPC900 Digital Controller for Advanced Light Control
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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DLPC900
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
www.ti.com
Product Folder Links: DLPC900
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
10.1.9 PCB Design Standards
PCB designed and built in accordance with the following industry specifications:
Table 19. Industry Design Specification
INDUSTRY SPECIFICATION
APPLICABLE TO
IPC-2221 and IPC2222, Type 3, Class X, at Level B producibility
Board Design
IPC-6011 and IPC-6012, Class 2
PWB Fabrication
IPC-SM-840, Class 3, Color Green
Finished PWB Solder mask
UL94V-0 Flammability Rating and Marking
Finished PWB
UL796 Rating and Marking
Finished PWB
(1)
Make width of GND trace as wide as the pin it is connected to, when possible.
(2)
Trace spacing of these signals/signal-pairs relative to other signals.
10.1.10 Signal Layers
The PCB signal layers should follow typical good practice guidelines including:
Layer changes should be minimized for single-ended signals.
Individual differential pairs can be routed on different layers, but the signals of a given pair should not change
layers.
Stubs should be avoided.
Only voltage or low-frequency signals should be routed on the outer layers, except as noted previously in this
document.
Double data rate signals should be routed first.
Pin swapping on components is not allowed.
The PCB should have a solder mask on the top and bottom layers. The mask should not cover the vias.
Except for fine pitch devices (pitch
≤ 0.032 inches), the copper pads and the solder mask cutout should be of
the same size.
Solder mask between pads of fine pitch devices should be removed.
In the BGA package, the copper pads and the solder mask cutout should be of the same size.
10.1.11 Trace Widths and Minimum Spacing
BGA escape routing can be routed with 4-mils width and 4-mils spacing, as long as the escape nets are less
than 1 inch long, to allow 2 traces fit between vias. After signals escape the BGA field, trace width should be
widened to achieve the desired impedance and spacing.
All single-ended 50-Ω signal must have a minimum spacing of 10mils relative to other signals. Other special
trace spacing requirements are listed in Table 20.
Table 20. Traces Widths and Minimum Spacing
SIGNAL ON PIN
MINIMUM WIDTH
MINIMUM SPACE
VDDC, VDD18, VDD33
0.020
0.015
GND
0.015 (1)
0.005
PLLS_VAD, PLLM2_VDD, PLLD_VDD,
PLLM1_VDD, PLLM1_VAD, PLLM2_VAD,
PLLD_VAD
0.012 (keep length less than 260 mils)
0.015
MOSCP, OCLKA
0.020 (2)
SCA_(P,N), DDA_(P,N)_(15:00), SCB_(P,N),
DDB_(P,N)_(15:00), DCKA_(P,N),
DCKB_(P,N)
0.030 (2)
USB_DAT_(P,N)
0.030 (2)




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