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SLC90E66-UF датащи(PDF) 11 Page - SMSC Corporation |
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SLC90E66-UF датащи(HTML) 11 Page - SMSC Corporation |
11 / 257 page SMSC DS – SLC90E66 Page 11 Rev. 07/10/2002 FIGURES FIGURE 1 - SYSTEM BLOCK DIAGRAM OF PC SYSTEM USING SLC90E66..........................................................13 FIGURE 2 – PC/PCI SERIAL DMA PROTOCOL.......................................................................................................163 FIGURE 3 - USB SYSTEM ........................................................................................................................................182 FIGURE 4 – OPENHCI FRAME BANDWIDTH ALLOCATION...................................................................................183 FIGURE 5 - PHYSICAL REGION DESCRIPTOR TABLE ENTRY.............................................................................189 FIGURE 6 - SLC90E66 SYSTEM CONFIGURATION ...............................................................................................195 FIGURE 7 - CLOCK CONTROL MECHANISMS (NON-BURST ENABLE)................................................................199 FIGURE 8 - CLOCK CONTROL MECHANISMS (BURST ENABLED) ......................................................................200 FIGURE 9 - STOP CLOCK EXAMPLE ......................................................................................................................201 FIGURE 10 - PCI CLOCK STOP TIMING..................................................................................................................202 FIGURE 11 – PCI CLOCK START TIMING ...............................................................................................................202 FIGURE 12 - PERIPHERAL DEVICE MANAGEMENT..............................................................................................203 FIGURE 13 - SLC90E66 POWER WELL TIMINGS ...................................................................................................224 FIGURE 14 - NRSMRST & PWROK TIMINGS..........................................................................................................224 FIGURE 15 – SUSPEND WELL POWER & NRSMRST ACTIVATED SIGNALS.......................................................225 FIGURE 16 – CORE WELL POWER & PWROK ACTIVATED SIGNALS..................................................................226 FIGURE 17 – CORE WELL POWER & PWROK ACTIVATED SIGNALS..................................................................228 FIGURE 18 – MECHANICAL OFF TO ON.................................................................................................................229 FIGURE 19 - ON TO POS .........................................................................................................................................230 FIGURE 20 - POS TO ON (W/ PROCESSOR & PCI RESET)...................................................................................231 FIGURE 21 - POS TO ON (W/ PROCESSOR RESET) .............................................................................................232 FIGURE 22 - POS TO ON (NO RESET)....................................................................................................................233 FIGURE 23 - ON TO STR..........................................................................................................................................234 FIGURE 24 - STR TO ON..........................................................................................................................................236 FIGURE 25 - ON TO STD / SOFF .............................................................................................................................237 FIGURE 26 - STD/ SOFF TO ON ..............................................................................................................................239 FIGURE 27 - POWER MANAGEMENT TIMER .........................................................................................................248 FIGURE 28 - SYSTEM MANAGEMENT BUS CONTROLLER ..................................................................................249 FIGURE 29 – PACKAGE DIMENSIONS....................................................................................................................251 FIGURE 30 – SLC90E66 324-BALL BGA BALL PATTERN ......................................................................................252 FIGURE 31 – SLC90E66 PIN ASSIGNMENT............................................................................................................253 TABLES Table 1 - General Purpose Input Signals .....................................................................................................................35 Table 2 - General Purpose Output Signals ..................................................................................................................36 Table 3 - Power Plane Descriptions .............................................................................................................................38 Table 4 - PCI Configuration Registers - Function 0 (PCI/ISA Bridge) ..........................................................................39 Table 5 - I/O Space Registers - Function 0 (ISA Compatibility) ...................................................................................40 Table 6 - PCI Bus Master IDE Controller Configuration Registers ...............................................................................43 Table 7 - PCI Bus Master IDE Controller I/O Space Registers ....................................................................................44 Table 8 - PCI Configuration Register Summary ...........................................................................................................44 Table 9 – USB HC Operational Register Summary......................................................................................................45 Table 10 - PCI COnfiguration Register Summary for Power Management (Function 3) ..............................................45 Table 11 - Ultra ATA/66 Timing Mode Settings ............................................................................................................94 Table 12 - DMA/PIO Timing Values (Based on SLC90E66 Cable Mode and System Speed) .....................................94 Table 13 - Interrupt/Activity Status Combinations ........................................................................................................96 Table 14 – Base Address Register.............................................................................................................................101 Table 15 - GPI to Device Monitor Translation ............................................................................................................123 Table 16 – Response to DMA and ISA Master Accesses to Main Memory Addresses..............................................155 Table 17 – PCI Accesses to BIOS Memory Spaces...................................................................................................156 Table 18 - ISA BIOS Memory Space..........................................................................................................................157 Table 19 - DMA Transfer Size Summary ...................................................................................................................161 Table 20 - Address Shifting for 16-bit DMA Transfers................................................................................................161 Table 21 - I/O Addresses for PC/PCI DMA Cycles.....................................................................................................164 Table 22 - Byte Enable and Address/Data Signal Usage for PC/PCI DMA................................................................165 Table 23 - Mapping of 8237 Registers to Distributed DMA Peripherals .....................................................................166 Table 24 - SERIRQ Frames .......................................................................................................................................172 Table 25 - RTC Standard RAM Bank .........................................................................................................................176 Table 26 - Internal and External RTC Usage .............................................................................................................176 Table 27 - USB Remote Wakeup Support .................................................................................................................184 Table 28 - IDE Legacy I/O Command Block (nCS1x) Definition ................................................................................187 |
Аналогичный номер детали - SLC90E66-UF |
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Аналогичное описание - SLC90E66-UF |
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