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SN74ABT16373DLR датащи(PDF) 1 Page - Texas Instruments |
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SN74ABT16373DLR датащи(HTML) 1 Page - Texas Instruments |
1 / 8 page SN54ABT16373, SN74ABT16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS469 - FEBRUARY 1991 - REVISED OCTOBER 1992 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Copyright © 1992, Texas Instruments Incorporated 1 • Members of the Texas Instruments Widebus ™ Family • State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 • Typical V OLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C • Distributed V CC and GND Pin Configuration Minimizes High-Speed Switching Noise • Flow-Through Architecture Optimizes PCB Layout • High-Drive Outputs (–32-mA I OH, 64-mA IOL) • Packaged in Plastic 300-mil Shrink Small-Outline Packages and 380-mil Fine-Pitch Ceramic Flat Packages Using 25-mil Center-to-Center Spacings description The 4ABT16373 is a 16-bit transparent D-type latch with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components The output enable (OE) does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74ABT16373 is available in TI’s shrink small-outline package (DL), which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN54ABT16373 is characterized for operation over the full military temperature range of – 55 °C to 125°C. The SN74ABT16373 is characterized for operation from – 40 °C to 85°C. SN54ABT16373 ...WD PACKAGE SN74ABT16373 ... DL PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE Widebus and EPIC- ΙΙB are trademarks of Texas Instruments Incorporated. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
Аналогичный номер детали - SN74ABT16373DLR |
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Аналогичное описание - SN74ABT16373DLR |
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