10
Am79213/Am79C203/031 Data Sheet
ASLAC Device
VLBIAS
Input
Longitudinal Offset Voltage. The input to this pin is the offset reference voltage for the
ASLIC device longitudinal control loop.
VREF
Input
Analog Reference. This voltage is provided by the ASLAC device and is used by the
ASLIC device for internal reference purposes. All analog input and output signals inter-
facing to the ASLAC device are referenced to this pin. Nominally set to 2.1 V.
VTX
Output
Four-Wire Transmit Signal. The voltage between this pin and VREF is a scaled version
of the AC component of the voltage sensed between the SA and SB pins. One end of the
two-wire input impedance programming network connects to VTX. The voltage at VTX
swings positive and negative about VREF.
Pin Names
Type
Description
AGND
Gnd
Analog (Quiet) Ground. VREF is referenced to this ground.
C2–C1
Output
ASLIC Device Control. These ternary logic output pins are dedicated to controlling the op-
erating state of the ASLIC device. The levels of these outputs are logic High, logic Low,
and high impedance.
CS
Input, Active
Low
Chip Select. The chip select input (active Low) enables the device so commands and
data can be written to or read from it. If chip select is held Low for 16 or more DCLK cy-
cles (independent of MCLK or PCLK), a hardware reset is executed at the time chip se-
lect returns to logic 1.
DCLK
Input
Data Clock. The data clock input shifts data into or out of the microprocessor interface of
the ASLAC device. The maximum clock rate is 4.096 MHz.
DGND
Gnd
Digital Ground. Digital ground return.
DI/O
Input/Output
Data Input/Output. Control data is serially written into and read out of the ASLAC device
via the DI/O pin, with the most significant bit first. The data clock (DCLK) determines the
data rate. DI/O is high impedance except when data is being transmitted from the ASLAC
device under control of CS.
DRA, DRB
Input
Receive PCM Data. Receive PCM data is received serially on either the DRA or DRB
port, with port selection under user program control. Data is received, most significant
bit first, in 8-bit PCM or 16-bit linear 2’s complement bursts every 125 µs at the PCLK
rate. The receive port is unaffected by the setting of the SMODE bit. (DRB – 44-pin
PLCC only.)
DXA, DXB
Output
Transmit PCM Data. Transmit PCM data is transmitted serially through either the DXA or
DXB port, with port selection under user control. The transmission data output is available
every 125 µs and is shifted out, most significant bit first, in 8-bit PCM or 16-bit linear 2’s
complement bursts at the PCLK rate. DXA/B are high impedance between bursts and
while the device is in the Inactive state.
For signaling register operation on the PCM highway, see the SMODE description. (DXB
– 44-pin PLCC only.)
FS
Input
Frame Sync. The frame sync signal is an 8 kHz pulse that identifies the beginning of a
frame. The ASLAC device references individual time slots with respect to this input, which
must be synchronized to PCLK.
IAB
Input
Loop Voltage Sense. The IAB pin is a current summing node referenced to VREF. An ex-
ternal resistor (RAB) is connected between this pin and the VDC pin of the ASLIC device,
In normal operation, current flows out of this pin. When the ASLIC device is in thermal
shutdown, current will be forced into this pin.
IBAT
Input
Battery Voltage Sense. The IBAT pin is a current summing node referenced to AGND and
receives a current that is proportional to the system battery voltage. A sense resistor/ca-
pacitor network is connected between the QBAT pin of the ASLIC device and the IBAT
pin.
Pin Names
Type
Description
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