поискавой системы для электроныых деталей |
|
CDCVF857 датащи(PDF) 7 Page - Texas Instruments |
|
|
CDCVF857 датащи(HTML) 7 Page - Texas Instruments |
7 / 19 page CDCVF857 2.5V PHASELOCK LOOP CLOCK DRIVER SCAS047D − MARCH 2003 − REVISED JUNE 2005 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT Without load fO = 170 MHz 120 140 Without load fO = 200 MHz 125 150 IDD Dynamic current on VDDQ Differential outputs terminated with fO = 170 MHz 220 270 mA IDD Dynamic current on VDDQ Differential outputs terminated with 120 Ω/CL = 0 pF fO = 200 MHz 230 280 mA Differential outputs terminated with fO = 170 MHz 280 330 Differential outputs terminated with 120 Ω/CL = 14 pF fO = 200 MHz 300 350 ∆C Part-to-part input capacitance variation VDDQ = 2.5 V, VI = VDDQ or GND 1 pF CI(∆) Input capacitance difference between CLK and CKB, FBIN, and FBINB VDDQ = 2.5 V, VI = VDDQ or GND 0.25 pF † All typical values are at a respective nominal VDDQ. timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN MAX UNIT fCLK Operating clock frequency 60 220 MHz fCLK Application clock frequency 90 220 MHz Input clock duty cycle 40% 60% Stabilization time{ (PLL mode) 10 µs Stabilization time} (bypass mode) 30 ns † The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK and VDD must be applied. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. ‡ A recovery time is required when the device goes from power-down mode into bypass mode (AVDD at GND). switching characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLHw Low-to-high level propagation delay time Test mode/CLK to any output 3.5 ns tPHLw High-to-low level propagation delay time Test mode/CLK to any output 3.5 ns tjit(per)W Jitter (period), See Figure 7 100 MHz (PC1600) −65 65 ps tjit(per)W Jitter (period), See Figure 7 133/167/200 MHz (PC2100/2700/3200) −30 30 ps tjit(cc)W Jitter (cycle-to-cycle), See Figure 4 100 MHz (PC1600) −50 50 ps tjit(cc)W Jitter (cycle-to-cycle), See Figure 4 133/167/200 MHz (PC2100/2700/3200) −35 35 ps tjit(hper)W Half-period jitter, See Figure 8 100 MHz (PC1600) −100 100 ps tjit(hper)W Half-period jitter, See Figure 8 133/167/200 MHz (PC2100/2700/3200) −75 75 ps tslr(o) Output clock slew rate, See Figure 9 Load: 120 Ω/14 pF 1 2 V/ns t(Ø) Static phase offset, See Figure 5 100/133/167/200 MHz –50 50 ps tsk(o) Output skew, See Figure 6 Load: 120 Ω/14 pF 100/133/167/200 MHz 40 ps § Refers to the transition of the noninverting output. ¶ This parameter is assured by design but can not be 100% production tested. |
Аналогичный номер детали - CDCVF857 |
|
Аналогичное описание - CDCVF857 |
|
|
ссылки URL |
Конфиденциальность |
ALLDATASHEETRU.COM |
Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |