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CS98200-EB датащи(PDF) 3 Page - Cirrus Logic

номер детали CS98200-EB
подробное описание детали  New Highly-Integrated Processor for Tommorrow DVD Players and DVD Receivers
Download  60 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS98200-EB датащи(HTML) 3 Page - Cirrus Logic

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DS581PP2
Copyright 2002 Cirrus Logic (All Rights Reserved)
3
CS98200
Next Generation DVD Processor
RIS C 0
RIS C 1
DS P
Au d io
In terfa ce
In stru ction
Cach e
Data
Cach e
CPU Pipe
MA C
In stru ction
Cach e
Data
Cach e
MA C
CPU Pipe
CPU/M A C
In stru ction
Cach e
X,Y D ata
Mem o ry
PC M O u t
PC M In
SP D IF O u t
DV D L o ad er I/O
MP E G D ec o d er
VL C
Pa rser
Motion
Com p
IDCT
RAM
D VD C ustom L oad er
Pa rallel/Seria l Da ta
Se rial C ontro l
AT AP I/G en eric
Pa ralle l Bu s Interfa ce
Ho s t Bus I/O
D ata flo w
E n gine
System C o n tro ls
N T SC /P A L En co d er
V ide o P ro ce ss o r
Su b p ic tu re
S R A M + CP U IF
System Syn c
Sim p le I/O
DRAM
Co ntro lle r
V ide o C ap ture
G rap h ics
DM A (R d + W r)
FL AS H
Mem ory.C o ntrol
ST C
Schedule
DM A (2)t
SR A M Bu ffer
D ecryptio n
M isc.
Reg ister
Ba nks
In te rrup t
PL L
PL L
Tim e rs
Dig ital
En coding
3 DACs
3 DACs
32 K Byte
In te rna l
SR A M
Arb iter
+
Con tro l
DM A
Deco de
r
Scaler
Line B uffe r
On Scre en D ispla y Ove rla y
Main V ideo
Scaling and D ispla y
Pictu re in P icture O ve rla y
Line B uffe r / F licke r F ilte r
Main G raphics
Deco de r
FIFO
SDRA M Con tro l
Vide o M ixin g
Dua l UART
PW M Sem i-D AC
2-W ire Se ria l (I2C)
3/4 W ire S erial (SP I)
Pro gra m m ab le I/O
In fra red Inp ut
PL L
MP E G 4 V id eo
D ec o d er Ac ce lera to r
CPU In te rfa ce
AL U + log ic
BLOCK DIAGRAM


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