поискавой системы для электроныых деталей |
|
FIN12AC датащи(PDF) 3 Page - Fairchild Semiconductor |
|
FIN12AC датащи(HTML) 3 Page - Fairchild Semiconductor |
3 / 21 page Preliminary 3 www.fairchildsemi.com Pin Description Note 1: The DSO/DSI serial port terminals have been arranged such that when one device is rotated 180 degrees with respect to the other device the serial connections will properly align without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross. Control Logic Circuitry The FIN12AC has the ability to be used as a 12-bit Serial- izer or a 12-bit Deserializer. Terminals S1 and S2 must be set to accommodate the clock reference input frequency range of the serializer. The table below shows the terminal programming of these options based on the S1 and S2 control terminals. The DIRI terminal controls whether the device is the serializer or a deserializer. When DIRI is asserted LOW, the device is configured as a deserializer. When the DIRI terminal is asserted HIGH, the device will be configured as a serializer. Changing the state on the DIRI signal will reverse the direction of the I/O signals and generate the opposite state signal on DIRO. For unidirec- tional operation the DIRI terminal should be hardwired to the HIGH or LOW state and the DIRO terminal should be left floating. For bi-directional operation the DIRI of the master device will be driven by the system and the DIRO signal of the master will be used to drive the DIRI of the slave device. Turn-Around Functionality The device passes and inverts the DIRI signal through the device asynchronously to the DIRO signal. Care must be taken by the system designer to insure that no contention occurs between the deserializer outputs and the other devices on this port. Optimally the peripheral device driving the serializer should be put into a HIGH Impedance state prior to the DIRI signal being asserted. When a device with dedicated data outputs turns from a deserializer to a serializer the dedicated outputs will remain at the last logical value asserted. This value will only change if the device is once again turned around into a deserializer and the values are overwritten. TABLE 1. Control Logic Circuitry Pin Name I/O Type Number of Pins Description of Signals DP[1:12] I/O 12 LVCMOS Parallel I/O. Direction controlled by DIRI terminal. CKREF IN 1 LVCMOS Clock Input and PLL Reference STROBE IN 1 LVCMOS Strobe Signal for Latching Data into the Serializer CKP OUT 1 LVCMOS Word Clock Output DSO / DSI DSO / DSI DIFF-I/O 2 CTL Differential Serial I/O Data Signals (Note ) DSO: Refers to output signal pair DSI: Refers to input signal pair DSO(I) : Positive signal of DSO(I) pair DSO(I) : Negative signal of DSO(I) pair CKSI , SKSI DIFF-IN 2 CTL Differential Deserializer Input Bit Clock CKSI: Refers to signal pair CKSI : Positive signal of CKSI pair CKSI : Negative signal of CKSI pair CKSO , CKSO DIFF-OUT 2 CTL Differential Serializer Output Bit Clock CKSO: Refers to signal pair CKSO : Positive signal of CKSO pair CKSO : Negative signal of CKSO pair S1 IN 1 LVCMOS Mode Selection terminals used to define S2 IN 1 frequency range for the RefClock, CKREF DIRI IN 1 LVCMOS Control Input Used to control direction of Data Flow: DIRI “1” Serializer, DIRI “0” Deserializer DIRO OUT 1 LVCMOS Control Output Inversion of DIRI VDDP Supply 1 Power Supply for Parallel I/O and Translation Circuitry VDDS Supply 1 Power Supply for Core and Serial I/O VDDA Supply 1 Power Supply for Analog PPL Circuitry GND Supply 0 Use Bottom Ground Plane for Ground Signals Mode Number S2 S1 DIRI Description 0 0 0 X Power-Down Mode 1 0 1 1 12-Bit Serializer, 20MHz to 56MHz CKREF 0 1 0 12-Bit Deserializer 2 1 0 1 12-Bit Serializer, 5MHz to 15MHz CKREF 1 0 0 12-Bit Deserializer 3 1 1 1 12-Bit Serializer, 10MHz to 30MHz CKREF 1 1 0 12-Bit Deserializer |
Аналогичный номер детали - FIN12AC |
|
Аналогичное описание - FIN12AC |
|
|
ссылки URL |
Конфиденциальность |
ALLDATASHEETRU.COM |
Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |