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SN74LS165D датащи(PDF) 3 Page - ON Semiconductor |
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SN74LS165D датащи(HTML) 3 Page - ON Semiconductor |
3 / 8 page SN74LS165 http://onsemi.com 3 LOGIC DIAGRAM PL CP1 P4 P6 P5 P7 CP2 P3 P1 P2 P0 DS PRESET S CP R C L Q0 Q0 PRESET S CP R C L Q1 Q1 PRESET S CP R C L Q2 Q2 PRESET S CP R C L Q3 Q3 PRESET S CP R C L Q4 Q4 PRESET S CP R C L Q5 Q5 PRESET S CP R C L Q6 Q6 PRESET S CP R C L Q7 Q7 14 1 2 6 3 4 5 11 12 10 13 15 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS 7 9 FUNCTIONAL DESCRIPTION The SN74LS165 contains eight clocked master/slave RS flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry. Parallel data enters when the PL signal is LOW. The parallel data can change while PL is LOW, provided that the recommended setup and hold times are observed. For clock operation, PL must be HIGH. The two clock inputs perform identically; one can be used as a clock inhibit by applying a HIGH signal. To avoid double clocking, however, the inhibit signal should only go HIGH while the clock is HIGH. Otherwise, the rising inhibit signal will cause the same response as a rising clock edge. The flip-flops are edge-triggered for serial operations. The serial input data can change at any time, provided only that the recommended setup and hold times are observed, with respect to the rising edge of the clock. TRUTH TABLE PL CP CONTENTS RESPONSE PL 1 2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 RESPONSE L X X P0 P1 P2 P3 P4 P5 P6 P7 Parallel Entry H L DS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Right Shift H H Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 No Change H L DS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Right Shift H H Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 No Change H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial |
Аналогичный номер детали - SN74LS165D |
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Аналогичное описание - SN74LS165D |
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