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SN74LS273N датащи(PDF) 4 Page - ON Semiconductor |
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SN74LS273N датащи(HTML) 4 Page - ON Semiconductor |
4 / 8 page SN74LS273 http://onsemi.com 4 1.3 V *The shaded areas indicate when the input is permitted to *change for predictable output performance. 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V CP D Qn ts(H) th(H) ts(L) th(L) 1/f max tPLH tPLH tPHL tPHL MR CP Qn Qn 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V trec tPHL tPLH tW 1.3 V 1.3 V 1.3 V * tW Figure 1. Clock to Output Delays, Clock Pulse Width, Frequency, Setup and Hold Times Data to Clock Figure 2. Master Reset to Output Delay, Master Reset Pulse Width, and Master Reset Recovery Time AC WAVEFORMS DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH data to the Q outputs. |
Аналогичный номер детали - SN74LS273N |
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Аналогичное описание - SN74LS273N |
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