TLC32040C, TLC32040I, TLC32041C, TLC32041I

ANALOG INTERFACE CIRCUITS

SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

8

POST OFFICE BOX 655303

reset

A reset function is provided to initiate serial communications between the AIC and DSP and allow fast,

cost-effective testing during manufacturing. The reset function initializes all AIC registers, including the control

register. After a negative-going pulse on RESET, the AIC is initialized. This initialization allows normal serial port

communications activity to occur between AIC and DSP (see AIC DX data word format section).

loopback

This feature allows the user to test the circuit remotely. In loopback, OUT + and OUT – are internally connected

to IN + and IN –. Thus, the DAC bits (d15 to d2), which are transmitted to DX, can be compared with the ADC

bits (d15 to d2), which are received from DR. An ideal comparison would be that the bits on DR equal the bits

on DX. However, in practice there is some difference in these bits due to the ADC and DAC output offsets.

In loopback, if IN + and N – are enabled, the external signals on IN + and IN – are ignored. If AUX IN + and AUX

IN – are enabled, the external signals on these terminals are added to the OUT + and OUT – signals in loopback

operation.

The loopback feature is implemented with digital signal processor control by transmitting the appropriate serial

port bit to the control register (see AIC DX data word format section).

explanation of internal timing configuration

All of the internal timing of the AIC is derived from the high-frequency clock signal that drives the master clock

input. The shift clock signal, which strobes the serial port data between the AIC and DSP, is derived by dividing

the master clock input signal frequency by four.

SCF Clock Frequency

+

Master Clock Frequency

2

Contents of Counter A

Conversion Frequency

+

SCF Clock Frequency

Contents of Counter B

Shift Clock Frequency

+

Master Clock Frequency

4

TX counter A and TX counter B, which are driven by the master clock signal, determine the D/A conversion

timing. Similarly, RX counter A and RX counter B determine the A/D conversion timing. In order for the

switched-capacitor low-pass and band pass filters to meet their transfer function specifications, the frequency

of the clock inputs of the switched-capacitor filters must be 288 kHz. If the frequencies of the clock inputs are

not 288 kHz, the filter transfer function frequencies are scaled by the ratios of the clock frequencies to 288 kHz.

Thus, to obtain the specified filter responses, the combination of master clock frequency and TX counter A and

RX counter A values must yield 288-kHz switched-capacitor clock signals. These 288-kHz clock signals can

then be divided by the TX counter B and RX counter B to establish the D/A and A/D conversion timings.

TX counter A and TX counter B are reloaded every D/A conversion period, while RX counter A and RX counter

B are reloaded every A/D conversion period. The TX counter B and RX counter B are loaded with the values

in the TB and RB registers, respectively. Via software control, the TX counter A can be loaded with either the

TA register, the TA register less the TA’ register, or the TA register plus the TA’ register. By selecting the TA

register less the TA’ register option, the upcoming conversion timing will occur earlier by an amount of time that

equals TA’ times the signal period of the master clock. By selecting the TA register plus the TA’ register option,

the upcoming conversion timing will occur later by an amount of time that equals TA’ times the signal period of

the master clock. Thus, the D/A conversion timing can be advanced or retarded. An identical ability to alter the

A/D conversion timing is provided. In this case, however, the RX counter A can be programmed via software

control with the RA register, the RA register less the RA’ register, or the RA register plus the RA’ register.