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CDC950DGG датащи(PDF) 1 Page - Texas Instruments |
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CDC950DGG датащи(HTML) 1 Page - Texas Instruments |
1 / 16 page CDC950 133MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Generates Clocks for Next Generation Microprocessors D Uses a 14.318-MHz Crystal Input to Generate Multiple Output Frequencies D Includes Spread Spectrum Clocking (SSC), 0.6% Downspread for Reduced EMI With Theoretical EMI of 7 dB D Power Management Control Terminals D Low Output Skew and Jitter for Clock Distribution D Operates From a Single 3.3-V Supply D Generates the Following Clocks: − 8 Host (Diff Pairs, 100/133 MHz) − 1 CLK33 (3.3 V, 33.3 MHz) − 1 REFCLK (3.3 V, 14.318 MHz) − 2 3V48 (3.3 V, 180 ° Shifted Pairs, 48 MHz) D Packaged in a 48-Pin TSSOP Package description The CDC950 is a differential clock synthesizer/ driver that generates HCLK/HCLK, CLK33, 3V48, and REFCLK system clock signals to support a computer system with next generation processors and double data rate (DDR) memory subsystems. All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided at the XIN input instead of a crystal. Two phase-locked loops (PLLs) are used to generate the host frequencies and the 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the need for external components. The HCLK, CLK33 clock, and 48-MHz clock outputs provide low-skew/low-jitter clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected through control inputs SEL100/133, 3V48/SelA, and 3V48/SelB. The outputs are either differential host clock or 3.3-V single-ended CMOS buffers. With a logic high-level on the PWRDWN terminal, the device operates normally. When a logical low-level input is applied, the device powers down completely with the HOST clock at 2 × IREF, HOSTB is undriven, CLK33, 3V48, and REFCLK outputs are in a low-level output state and 3V48B is in a high-level output state. The host bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with the corresponding setting for SEL100/133 control input. The CLK33 (PCI) frequency is fixed to 33 MHz. Since the CDC950 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up, as well as following changes to the SEL inputs. With the use of an external reference clock, this signal must be fixed-frequency and fixed-phase prior to stabilization time starts. The CDC950 is characterized for operation from 0 °C to 85°C. Copyright 2001 − 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 CLK33 VDD3.3V 3V48/SelA 3V48/SelB GND VDD3.3V HCLK(0) HCLK(0) GND HCLK(1) HCLK(1) VDD3.3V HCLK(2) HCLK(2) GND HCLK(3) HCLK(3) VDD3.3V REFCLK SPREAD GND XIN XOUT VDD3.3V SEL100/133 GND AVDD3.3V AGND PWRDWN VDD3.3V HCLK(4) HCLK(4) GND HCLK(5) HCLK(5) VDD3.3V HCLK(6) HCLK(6) GND HCLK(7) HCLK(7) VDD3.3V MultSel0 MultSel1 GND AGND I_REF AVDD3.3V DGG PACKAGE (TOP VIEW) |
Аналогичный номер детали - CDC950DGG |
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Аналогичное описание - CDC950DGG |
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