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AD8316ARM-REEL7 датащи(PDF) 11 Page - Analog Devices |
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AD8316ARM-REEL7 датащи(HTML) 11 Page - Analog Devices |
11 / 20 page REV. C AD8316 –11– volts rms; and VZ is the effective intercept voltage, which, as previously noted, is dependent on waveform but is 199 µV rms for a sine wave input. Now, the current generated by the setpoint interface is simply IV k SET SET =Ω /. 415 (4) IERR, the difference between this current and IDET, is applied to the loop filter capacitor CFLT. It follows that the voltage appearing on this capacitor, VFLT, is the time integral of the difference current Vs I I sC FLT SET DET FLT () ( – ) / = (5) = Ω Vk IV V sC SET SLP IN Z FLT /. – log ( / ) 415 10 (6) The control output VOUT is slightly greater than this, since the gain of the output buffer is ×1.35. Also, an offset voltage is delib- erately introduced in this stage, but this is inconsequential, since the integration function implicitly allows for an arbitrary constant to be added to the form of Equation 6. The polarity is such that VOUT will rise to its maximum value for any value of VSET greater than the equivalent value of VIN. In practice, the output will rail to the positive supply under this condition unless the control loop through the power amplifier is present. In other words, the AD8316 seeks to drive the RF power to its maximum value when- ever it falls below the setpoint. The use of exact integration results in a final error that is theoretically zero, and the logarithmic detection law would ideally result in a constant response time following a step change of either the setpoint or the power level, if the power amplifier control function were likewise “linear-in-dB.” This latter condition is rarely true, however, and it follows that the loop response time will, in practice, depend on the power level, and this effect can strongly influence the design of the control loop. Equation 6 can be clarified by noting that it can be restated in the following way Vs VV V V sT OUT SET SLP IN Z () – log ( / ) = 10 (7) where VSLP is the volts-per-decade slope from Equation 1, having a value of 440 mV/dec, and T is an effective time constant for the integration, being equal to (4.15 k Ω × C FLT)/1.35; the resis- tor value comes from the setpoint interface scaling Equation 4 and the factor 1.35 arises as a result of the voltage gain of the buffer. So the integration time constant can be written as TC in s when C is ressed in nF FLT FLT =× () 307 . µ exp (8) To simplify understanding of the control loop dynamics, begin by assuming that the power amplifier gain function actually is linear-in-dB; for now, we will also use voltages to express the signals at the power amplifier input and output. Let the RF output voltage be VPA and its input be VCW; further, to characterize the gain control function, this form is used VG V PA O CW = 10 (/ ) VV OUT GSC (9) where GO is the gain of the power amplifier when VOUT = 0 and VGSC is the gain scaling. While few amplifiers will conform so conveniently to this law, it nevertheless provides a clearer starting point for understanding the more complex situation that arises when the gain control law is less than ideal. This idealized control loop is shown in Figure 4. With some manipulation, it is found that the characteristic equation of this system is Vs VV V V kG V V sT OUT SET GSC SLP GSC O CW Z O () ()/ log ( / ) = − + 10 1 (10) where k is the voltage coupling factor from the output of the power amplifier to the input of the AD8316 (e.g., ×0.1 for a 20 dB coupler) and TO is a modified time constant (VGSC/VSLP)T. This is quite easy to interpret. First, it shows that a system of this sort will exhibit a simple single-pole response, for any power level, with the customary exponential time domain form for either increasing or decreasing step polarities in the demand level VSET or the carrier input VCW. Second, it reveals that the final value of the control voltage VOUT will be determined by several fixed factors Vt V V V V kG V V OUT SET GSC SLP GSC O CW Z =∞ () =− ()/ log ( / ) 10 (11) RF PA VCW RF DRIVE: UP TO 2.5GHz VRF DIRECTIONAL COUPLER CFLT AD8316 RESPONSE-SHAPING OF OVERALL CONTROL LOOP (EXTERNAL CAP) VSET VIN = kVRF VOUT1 Figure 4. Idealized Control Loop for Dynamic Analysis, OUT1 Selected Example Assume that the gain magnitude of the power amplifier runs from a minimum value of ×0.316 (–10 dB) at V OUT = 0 to ×100 (40 dB) at VOUT = 2.5 V. Applying Equation 9, we find GO = 0.316 and VGSC = 1 V. Using a coupling factor of k = 0.0316 (that is, a 30 dB directional coupler) and recalling that the nominal value of VSLP is 440 mV and VZ = 199 µV for the AD8316, we will first calculate the range of values needed for VSET to control an output range of +32 dBm to –17 dBm. Note that, in the steady state, the numerator of Equation 7 must be zero, that is VV kV V SET SLP PA Z = () log 10 (12) when VIN is expanded to kVPA, the fractional voltage sample of the power amplifier output. Now, for +32 dBm, VPA = 8.9 V rms, this evaluates to V max mV/ V V SET () = () = 044 281 199 139 10 . log . µ (13) For a delivered power of –17 dBm, VPA = 31.6 mV rms, V min . mV/ V V SET () = () = 044 1 0 199 0 310 10 . log . µ (14) Note: The power range is 49 dB, which corresponds to a voltage change of 49 dB × 22 mV/dB = 1.08 V in V SET. |
Аналогичный номер детали - AD8316ARM-REEL7 |
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Аналогичное описание - AD8316ARM-REEL7 |
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