GS88218/36BB/D-333/300/250/200/150

Rev: 1.02 10/2004

9/37

© 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Note:

There pull-down device on the ZZ pin, so input pin can be unconnected and the chip will operate in the default states as specified in the above

tables.

Burst Counter Sequences

BPR 1999.05.18

Mode Pin Functions

Mode Name

Pin Name

State

Function

Burst Order Control

LBO

L

Linear Burst

H

Interleaved Burst

Power Down Control

ZZ

L or NC

Active

H

Note:

The burst counter wraps to initial state on the 5th clock.

Note:

The burst counter wraps to initial state on the 5th clock.

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

00

01

10

11

2nd address

01

10

11

00

3rd address

10

11

00

01

4th address

11

00

01

10

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

00

01

10

11

2nd address

01

00

11

10

3rd address

10

11

00

01

4th address

11

10

01

00