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4 / 63 page November 7, 2002 Am50DL128CG 3 P R E L I M I NARY TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5 Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7 Special Package Handling Instructions .................................... 7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 MCP Device Bus Operations . . . . . . . . . . . . . . . . 10 Table 1. Device Bus Operations—Flash Word Mode ..................... 11 Flash Device Bus Operations . . . . . . . . . . . . . . . 12 Word Configuration ................................................................. 12 Requirements for Reading Array Data ................................... 12 Writing Commands/Command Sequences ............................ 12 Accelerated Program Operation .......................................... 12 Autoselect Functions ........................................................... 12 Simultaneous Read/Write Operations with Zero Latency ....... 12 Standby Mode ........................................................................ 12 Automatic Sleep Mode ........................................................... 13 RESET#: Hardware Reset Pin ............................................... 13 Output Disable Mode .............................................................. 13 Table 2. Am29DL640G Sector Architecture ....................................14 Table 3. Bank Address ....................................................................17 Table 4. SecSi Sector Addresses ...............................................17 Sector/Sector Block Protection and Unprotection .................. 18 Table 5. Am29DL640G Boot Sector/Sector Block Addresses for Pro- tection/Unprotection ........................................................................18 Write Protect (WP#) ................................................................ 18 Table 6. WP#/ACC Modes ..............................................................19 Temporary Sector Unprotect .................................................. 19 Figure 1. Temporary Sector Unprotect Operation........................... 19 Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 20 SecSi™ (Secured Silicon) Sector Flash Memory Region ............................................................ 21 Figure 3. SecSi Sector Protect Verify.............................................. 22 Hardware Data Protection ...................................................... 22 Low V CC Write Inhibit ........................................................... 22 Write Pulse “Glitch” Protection ............................................ 22 Logical Inhibit ...................................................................... 22 Power-Up Write Inhibit ......................................................... 22 Common Flash Memory Interface (CFI) . . . . . . . 22 Table 7. CFI Query Identification String .......................................... 23 System Interface String................................................................... 23 Table 9. Device Geometry Definition .............................................. 24 Table 10. Primary Vendor-Specific Extended Query ...................... 25 Flash Command Definitions . . . . . . . . . . . . . . . . 26 Reading Array Data ................................................................ 26 Reset Command ..................................................................... 26 Autoselect Command Sequence ............................................ 26 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence .............................................................. 26 Word Program Command Sequence ..................................... 27 Unlock Bypass Command Sequence .................................. 27 Figure 4. Program Operation .......................................................... 28 Chip Erase Command Sequence ........................................... 28 Sector Erase Command Sequence ........................................ 28 Figure 5. Erase Operation............................................................... 29 Erase Suspend/Erase Resume Commands ........................... 29 Table 11. Am29DL640G Command Definitions .............................. 30 Flash Write Operation Status . . . . . . . . . . . . . . . 31 DQ7: Data# Polling ................................................................. 31 Figure 6. Data# Polling Algorithm .................................................. 31 RY/BY#: Ready/Busy# ............................................................ 32 DQ6: Toggle Bit I .................................................................... 32 Figure 7. Toggle Bit Algorithm........................................................ 32 DQ2: Toggle Bit II ................................................................... 33 Reading Toggle Bits DQ6/DQ2 ............................................... 33 DQ5: Exceeded Timing Limits ................................................ 33 DQ3: Sector Erase Timer ....................................................... 33 Table 12. Write Operation Status ................................................... 34 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35 Figure 8. Maximum Negative Overshoot Waveform ...................... 35 Figure 9. Maximum Positive Overshoot Waveform........................ 35 Flash DC Characteristics . . . . . . . . . . . . . . . . . . 36 CMOS Compatible .................................................................. 36 Figure 10. I CC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ............................................................. 38 Figure 11. Typical I CC1 vs. Frequency ............................................ 38 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 12. Test Setup.................................................................... 39 Figure 13. Input Waveforms and Measurement Levels ................. 39 pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 40 CE#s Timing ........................................................................... 40 Figure 14. Timing Diagram for Alternating Between Pseudo SRAM to Flash................................................... 40 Read-Only Operations ........................................................... 41 Figure 15. Read Operation Timings ............................................... 41 Hardware Reset (RESET#) .................................................... 42 Figure 16. Reset Timings ............................................................... 42 Erase and Program Operations .............................................. 43 Figure 17. Program Operation Timings.......................................... 44 Figure 18. Accelerated Program Timing Diagram .......................... 44 Figure 19. Chip/Sector Erase Operation Timings .......................... 45 Figure 20. Back-to-back Read/Write Cycle Timings ...................... 46 Figure 21. Data# Polling Timings (During Embedded Algorithms). 46 Figure 22. Toggle Bit Timings (During Embedded Algorithms)...... 47 Figure 23. DQ2 vs. DQ6................................................................. 47 Temporary Sector Unprotect .................................................. 48 Figure 24. Temporary Sector Unprotect Timing Diagram .............. 48 Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram ............................................................. 49 Alternate CE#f Controlled Erase and Program Operations .... 50 Figure 26. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings.......................................................................... 51 Read Cycle ............................................................................. 52 Figure 27. Pseudo SRAM Read Cycle........................................... 52 Figure 28. Page Read Timing ........................................................ 53 Write Cycle ............................................................................. 54 Figure 29. Pseudo SRAM Write Cycle—WE# Control ................... 54 Figure 30. Pseudo SRAM Write Cycle—CE1#s Control ................ 55 Figure 31. Pseudo SRAM Write Cycle— UB#s and LB#s Control.................................................................. 56 Flash Erase And Programming Performance . . 57 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 57 Package Pin Capacitance. . . . . . . . . . . . . . . . . . . 57 Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 57 |
Аналогичный номер детали - AM50DL128CG70IT |
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Аналогичное описание - AM50DL128CG70IT |
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