поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

GS8321ZV32E-150I датащи(PDF) 7 Page - GSI Technology

номер детали GS8321ZV32E-150I
подробное описание детали  36Mb Pipelined and Flow Through Synchronous NBT SRAM
Download  31 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  GSI [GSI Technology]
домашняя страница  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8321ZV32E-150I датащи(HTML) 7 Page - GSI Technology

Back Button GS8321ZV32E-150I Datasheet HTML 3Page - GSI Technology GS8321ZV32E-150I Datasheet HTML 4Page - GSI Technology GS8321ZV32E-150I Datasheet HTML 5Page - GSI Technology GS8321ZV32E-150I Datasheet HTML 6Page - GSI Technology GS8321ZV32E-150I Datasheet HTML 7Page - GSI Technology GS8321ZV32E-150I Datasheet HTML 8Page - GSI Technology GS8321ZV32E-150I Datasheet HTML 9Page - GSI Technology GS8321ZV32E-150I Datasheet HTML 10Page - GSI Technology GS8321ZV32E-150I Datasheet HTML 11Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 31 page
background image
GS8321ZV18/32/36E-250/225/200/166/150/133
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
7/31
© 2003, Giga Semiconductor, Inc.
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (BA, BB, BC & BD) determine which bytes will be written. All or none may be activated. A write cycle
with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the
third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Function
W
BA
BB
BC
BD
Read
H
X
X
X
X
Write Byte “a”
L
L
H
H
H
Write Byte “b”
L
H
L
H
H
Write Byte “c”
L
H
H
L
H
Write Byte “d”
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort/NOP
L
H
H
H
H


Аналогичный номер детали - GS8321ZV32E-150I

производительномер деталидатащиподробное описание детали
logo
GSI Technology
GS8321Z18 GSI-GS8321Z18 Datasheet
1Mb / 34P
   36Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8321Z18AD-150IV GSI-GS8321Z18AD-150IV Datasheet
305Kb / 32P
   36Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8321Z18AD-150V GSI-GS8321Z18AD-150V Datasheet
305Kb / 32P
   36Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8321Z18AD-200IV GSI-GS8321Z18AD-200IV Datasheet
305Kb / 32P
   36Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8321Z18AD-200V GSI-GS8321Z18AD-200V Datasheet
305Kb / 32P
   36Mb Pipelined and Flow Through Synchronous NBT SRAM
More results

Аналогичное описание - GS8321ZV32E-150I

производительномер деталидатащиподробное описание детали
logo
List of Unclassifed Man...
GS8320Z36T-166 ETC-GS8320Z36T-166 Datasheet
643Kb / 24P
   36Mb Pipelined and Flow Through Synchronous NBT SRAM
logo
GSI Technology
GS8321Z36AGD-250IV GSI-GS8321Z36AGD-250IV Datasheet
305Kb / 32P
   36Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8322Z18 GSI-GS8322Z18 Datasheet
763Kb / 38P
   36Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8322Z18B-V GSI-GS8322Z18B-V Datasheet
1Mb / 39P
   36Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8321Z18 GSI-GS8321Z18 Datasheet
1Mb / 34P
   36Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8322ZV18B GSI-GS8322ZV18B Datasheet
1Mb / 39P
   36Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8320Z18T GSI-GS8320Z18T Datasheet
463Kb / 24P
   36Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS8320Z18T-V GSI-GS8320Z18T-V Datasheet
1,013Kb / 23P
   36Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS8321Z18E GSI-GS8321Z18E Datasheet
1Mb / 34P
   36Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS8320ZV18T GSI-GS8320ZV18T Datasheet
606Kb / 23P
   36Mb Pipelined and Flow Through Synchronous NBT SRAMs
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31


датащи скачать

Go To PDF Page


ссылки URL




Конфиденциальность
ALLDATASHEETRU.COM
Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com