Limits in standard typeface are for T

less otherwise specified: V

Ω; BankA,

BankB, and DKEY = Fullscale Current; ENA, ENB, ENK Bits = “1”; C1=C2=1.0µF, C

output current(s) and current setting pins (I

Symbol

Parameter

Condition

Min

Typ

Max

Units

V

HR

Current Source Headroom Voltage

Requirement

(Note 11)

I

(I

≈ 15mA)

BankA and/or BankB Full-Scale

Gain = 3/2, ENA and/or ENB = "1"

180

mV

I

(I

≈ 60mA)

DKEY Full-Scale

Gain = 3/2, ENK = "1"

180

I

(Note 12)

0.2

2

%

I

Q

Quiescent Supply Current

Gain = 1.5x, No Load

1.3

1.7

mA

I

SD

Shutdown Supply Current

All ENx bits = "0"

3.0

5

µA

V

SET

I

2.7V

≤ V

IN

≤ 5.5V

1.25

V

I

DxA-B /

I

SETA-B

Output Current to Current Set

Ratio BankA and BankB

200

I

I

SETK

Output Current to Current Set

Ratio DKEY

800

f

SW

Switching Frequency

500

700

900

kHz

t

START

Start-up Time

P

250

µs

f

PWM

Internal Diode Current PWM

Frequency

LM27964SQ-I

10

kHz

LM27964SQ-A

23

D.C. Step Diode Current Duty Cycle Step

1/16

Fullscale

I

V

IO

Serial Bus Voltage Level

1.8

V

IN

V

V

IL

Input Logic Low "0"

2.7V

≤ V

IN

≤ 5.5V

0

0.27 x

V

IO

V

V

IH

Input Logic High "1"

2.7V

≤ V

IN

≤ 5.5V

0.73 x

V

IO

V

IO

V

V

OL

Output Logic Low "0"

I

400

mV

I

t

1

SCL (Clock Period)

2.5

µs

t

2

Data In Setup Time to SCL High

100

ns

t

3

Data Out stable After SCL Low

0

ns

t

4

SDIO Low Setup Time to SCL Low

(Start)

100

ns

t

5

SDIO High Hold Time After SCL

High (Stop)

100

ns

20138113

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