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GS1501 датащи(PDF) 5 Page - Gennum Corporation |
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GS1501 датащи(HTML) 5 Page - Gennum Corporation |
5 / 15 page GENNUM CORPORATION 52234 - 4 5 13 TRS_INS Non- synchronous Input Control Signal Input. Used to enable or disable insertion of TRS into the video streams. When TRS_INS is high, the device inserts SMPTE 292M compliant TRS signals into the input LUMA and CHROMA data streams based on the supplied HVF signals. When TRS_INS is low, the device does not insert TRS signals. 15 LN_INS Non- synchronous Input Control Signal Input. Used to enable or disable insertion of line numbers into the video stream. When LN_INS is high, the device inserts SMPTE 292M compliant line number information into the LUMA and CHROMA channels. When LN_INS is low, the device does not insert the line number information into the LUMA and CHROMA channels. Line number insertion is only available when user supplied external FVH data is used (DET_TRS set LOW). 16 CRC_INS Non- synchronous Input Control Signal Input. Used to enable or disable insertion of CRC's into the video stream. When CRC_INS is high, the device calculates and inserts line based CRCs. When CRC_INS is low, this feature is disabled. 21 H Synchronous wrt PCLK_IN Input Control Signal Input. This signal indicates the Horizontal blanking period of the input video data stream. The device inserts HDTV TRS based on the supplied HVF signals. Refer to Figure 4 for required timing of H relative to LUMA (DATA_IN[19:10]) and CHROMA (DATA_IN[9:0]). 22 V Synchronous wrt PCLK_IN Input Control Signal Input. This signal indicates the vertical blanking period of the input video data streams. Refer to Figure 4 for required timing of V relative to LUMA (DATA_IN[19:10]) and CHROMA (DATA_IN[9:0]). 23 F Synchronous wrt PCLK_IN Input Control Signal Input. This signal indicates the ODD/EVEN field of the input video data streams. Refer to Figure 4 for required timing of F relative to LUMA (DATA_IN[19:10]) and CHROMA (DATA_IN[9:0]). When the input video format is progressive scan, F should remain low at all times. 26, 27, 28, 29, 30, 31, 32, 33, 34, 65, 66, 67, 71, 72, NC N/A No Connect. Do not connect these pins 35 TN N/A TEST Test Pin. Used for test purposes only. This pin must be connected to VDD for normal operation 36 OEN See A/C Electrical Characteristic s section Input Control Signal Input. Used to enable DATA_OUT[19:0] output bus or set it to a high Z state. When OEN is low, the DATA_OUT[19:0] bus is enabled. When OEN is high, the DATA_OUT[19:0] bus is disabled and in a high Z state. 64, 63, 62, 61, 60, 57, 56, 55, 54, 53, 52, 49, 48, 45, 44, 43, 42, 41, 40, 39 DATA_OUT[19:0] Synchronous wrt PCLK_IN Outputs Output Data Bus. The device generates a 20 bit wide data stream running at 74.25 (or 74.25/1.001) MHz. DATA_OUT[19] is the MSB and DATA_OUT[0] is the LSB. 70 TEST N/A TEST Test Pin. Used for test purposes only. This pin must be connected to GND for normal operation. 1.2 PIN DESCRIPTIONS (Continued) (Continued) (Continued) (Continued) PIN NUMBER NAME TIMING TYPE DESCRIPTION |
Аналогичный номер детали - GS1501 |
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Аналогичное описание - GS1501 |
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