9 of 12

32466 - 0

NOT

RECOMMENDED

FOR

NEW

DESIGNS

TEST SETUP

Figure 14 shows a typical circuit for the GS9005B using a +5

volt supply. The four 0.1µF decoupling capacitors must be

placed as close as possible to the corresponding V

CC

pins.

The loop voltage can be conveniently measured across the

10nF capacitor in the loop filter. Tuning procedures are

described in the Temperature Compensation Section

(page 11). The fixed value frequency setting resistors should

be placed close to the corresponding pins on the GS9005B.

The layout of the loop filter and RVCO components requires

careful attention. This has been detailed in an application

note entitled "Optimizing Circuit and Layout Design of the

GS9005A/15A", Document No. 521 - 32 - 00.

When the Direct Digital Inputs are not used, one of these

inputs should be connected to V

CC

to avoid picking up noise

and unwanted signals.

The Carrier Detect is an open-collector active high output

requiring a pull-up resistor of approximately 10 k

Ω.

The SS0, SS1, CD pins should see a low AC impedance. This

is particularly important when driving the SS0, SS1 pins with

external logic. The use of 1 nF decoupling capacitors at these

pins ensures this.

Figure 15 shows the GS9005B connections when using a -5

volt supply.

Fig.14 GS9005B Typical Test Circuit Using +5V Supply

All resistors in ohms, all capacitors in microfarads, all inductors in henries unless otherwise stated.

+

ECL

DATA

INPUTS

0.1µ

100

100

100

100

390

390

DATA

DATA

CLOCK

CLOCK

390

390

0.1µ

10µ

0.1µ

25

24

23

22

21

20

19

5

6

7

8

9

10

11

4

3

2

1 28 27 26

12 13 14 15 16 17 18

910

22n

75

113

75

47p

5.6p

10n

+5V

÷1

÷2

0.1µ

47p

0.1µ

10k

CARRIER

DETECT

OUTPUT

See Figure 18

+5V

+5V

+5V

+5V

INPUT

GS9005B

DD

I

DD

I

VCC2

SD

I

SD

I

ƒ/2

VEE3

SDO

SDO

SCO

SCO

SS1

SS0

CD

SSI

STAR

ROUTED

LOOP

VOLTAGE

TEST

POINT

ANALOG

+5V

DIGITAL