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GS9004DCKBE3 датащи(PDF) 3 Page - Gennum Corporation

номер детали GS9004DCKBE3
подробное описание детали  GENLINX-TM GS9004D Serial Digital Cable Equalizer
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производитель  GENNUM [Gennum Corporation]
домашняя страница  http://www.gennum.com
Logo GENNUM - Gennum Corporation

GS9004DCKBE3 датащи(HTML) 3 Page - Gennum Corporation

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32486 -0
NOT
RECOMMENDED
FOR
NEW
DESIGNS
This output is integrated by an external AGC filter capacitor
(AGC CAP pin 7), providing a steady control voltage for the
voltage variable filter.
A separate signal strength indicator output, (SSI pin 6),
proportional to the amount of AGC, is also provided. As the
filter characteristic is varied automatically by the application
of negative feedback, the amplitude of the equalized signal is
kept at a constant level which is representative of the original
amplitude at the transmitter.
The equalized signal is then DC restored, effectively restoring
the logic threshold of the equalized signal to its correct level
irrespective of shifts due to AC coupling.
As the final stage of signal conditioning, a comparator converts
the analog output of the DC restorer to a regenerated digital
output signal having pseudo-ECL voltage levels. These
outputs, DATA and DATA, are available from pins 13 and 14
respectively.
An OUTPUT 'EYE' MONITOR (pin 3) allows verification of
signal integrity after equalization, prior to reslicing.
GS9004D CABLE EQUALIZER - DETAILED DEVICE DESCRIPTION
The GS9004D Cable Equalizer is a bipolar integrated circuit
used to equalize SMPTE 259M signals from a co-axial cable.
The device is implemented as a fourteen pin SOIC, powered
from a single five volt supply. With an operating frequency up
to 400 Mb/s, the equalizer consumes about 285 mW of
power.
The Serial Digital signal is connected to the input (pins 8, 9)
either differentially or single ended with the unused input
being decoupled.
The equalized signal is generated by
passing the cable signal through a voltage variable filter
having a characteristic which closely matches the inverse
cable loss characteristic. Additionally, the variation of the
filter characteristic with control voltage is designed to imitate
the variation of the inverse cable loss characteristic as the
cable length is varied.
The amplitude of the equalized signal is monitored by a peak
detector circuit which produces an output current with a
polarity corresponding to the difference between the desired peak
signal level and the actual peak signal level.
Fig. 2 Test Set-up 1
All resistors in ohms, all capacitors in microfarads,
all inductors in henries unless otherwise stated.
DATA
CLOCK
D.U.T.
CABLE
DRIVER
CABLE
DRIVER
OSCILLOSCOPE
VERTICAL
IN
TRIGGER
IN
8281 CABLE
ANRITSU
ME522A
OR
TEKTRONIX
TSG422
Fig. 1 Test Circuit
18n
75
4
3
2
1
5
6
7
8
150
1.0
68
1.8p
1.8p
1.0
100
113
100
680
680
68
150
1.8p
1.0
68
150
VCC
VCC
VCC
VCC
VCC
VCC
VCC
1.0
68
1.8p
150
SDO4
SDO3
SDO2
SDO1
GS9007
50
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SDI
OEM
47p
47p
75
GS9004D
OEM
SSI
100n
100n
100n
100n
100n
10µ
+
100n
10
+
100n
VCC
VCC
OEM
VCC
N/C
SSI
AGC
DATA
DATA
GND1
GND
GND
IN -
IN+
GND
+5V
SO2
SO2
SO1
SO1
GND
SI
SI
VCC


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