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SI3225-X-FQ датащи(PDF) 4 Page - Silicon Laboratories

номер детали SI3225-X-FQ
подробное описание детали  DUAL PROSLIC짰 PROGRAMMABLE CMOS SLIC/CODEC
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Si3220/25
4
Rev. 1.2
1. Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information1
Parameter
Symbol
Test
Condition
Value
Unit
Supply Voltage, Si3200 and Si3220/Si3225
VDD, VDD1–VDD4
–0.5 to 6.0
V
High Battery Supply Voltage, Si32002
VBATH
Continuous
0.4 to –104
V
10 ms
0.4 to –109
Low Battery Supply Voltage, Si3200
VBAT,VBATL
Continuous
VBATH
V
TIP or RING Voltage, Si3205
VTIP,VRING
Continuous
Pulse < 10 µs
Pulse < 4 µs
–104
VBATH –15
VBATH –35
TIP, RING Current, Si3200
ITIP, IRING
±100
mA
STIPAC, STIPDC, SRINGAC, SRINGDC Current,
Si3220/Si3225
±20
mA
Input Current, Digital Input Pins
IIN
Continuous
±10
mA
Si3220/25 Analog Ground Differential Voltage
(GND1 to ePad, GND2 to ePad, or GND1 to GND2)3
∆VGNDA
±50
mV
Si3220/25 Digital Ground Differential Voltage (GND3
to GND4)3
∆VGNDD
±50
mV
Si3220/25 Analog to Digital Ground Differential Volt-
age (GND1/GND2/ePad to GND3/GND4)3
∆VGND,A–D
±200
mV
Digital Input Voltage
VIND
–0.3 to (VDDD + 0.3)
V
Operating Temperature Range
TA
–40 to 100
°C
Storage Temperature Range
TSTG
–40 to 150
°C
Si3220/Si3225 Thermal Resistance,
Typical3 (TQFP-64 ePad)
θJA
25
°C/W
Si3200 Thermal Resistance, Typical4
(SOIC-16 ePad)
θJA
55
°C/W
Continuous Power Dissipation, Si32005
PD
TA =85°C,
SOIC-16
1W
Continuous Power Dissipation, Si3220/25
PD
TA =85°C,
TQFP-64
1.6
W
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. The dv/dt of the voltage applied to the VBAT, VBATH, and VBATL pins must be limited to 10 V/µs.
3. The PCB pad placed under the device package must be connected with multiple vias to the PCB ground layer and to the
GND1-GND4 pins via short traces. The TQFP-64 e-Pad must be properly soldered to the PCB pad during PCB
assembly. This type of low-impedance grounding arrangement is necessary to ensure that maximum differentials are not
exceeded under any operating condition in addition to providing thermal dissipation.
4. The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout
guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed
copper surface of equal size and that multiple vias are added to enable heat transfer between the top-side copper
surface and a large internal copper ground plane. Refer to “AN55: Dual ProSLIC® User Guide” or to the Si3220/3225
evaluation board data sheet for specific layout examples.
5. On-chip thermal limiting circuitry will shut down the circuit at a junction temperature of approximately 150 °C. For optimal
reliability, junction temperatures above 140 °C should be avoided.


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