GS8161FZ18/32/36BD

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.00 6/2006

7/28

© 2006, GSI Technology

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to

suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Flow Through Mode Read and Write Operations

Flow Through NBT SRAMs are equipped with rising-edge-triggered input registers that capture data-in, address, and control input

signals, but do not have a data output register like the one found on pipelined NBT SRAMs. Once a read command and an

associated read address is clocked into the RAM, the read operation proceeds and, if the Output Enable pin is driven active low,

culminates with the read data appearing on the RAM output pins, even if no additional clocks are sent to the RAM.

A write operation in a Flow Through NBT SRAM begins when a write command and write address are clocked into the RAM.

Next, data-in for that write address must be applied to the input pins and held for capture by the very next rising edge of clock. A

write protocol like the one used on Flow Through NBT SRAMs—the capture of the write address and write command on one clock

and the capture of the write data-in on the next clock—is often described as a Late Write protocol.

It is the combination of the Flow Through read protocol and the Late Write write protocol that allows the Flow Through NBT

SRAM to achieve seamless back-to-back, read-write-read transitions on a bi-directional data bus without requiring the user to

insert dead cycles to prevent bus contention during the transition from read to write or write to read.