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GS8182S18GD-200I датащи(PDF) 3 Page - GSI Technology |
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GS8182S18GD-200I датащи(HTML) 3 Page - GSI Technology |
3 / 31 page Pin Description Table Symbol Description Type Comments SA Synchronous Address Inputs Input — NC No Connect — — R/W Synchronous Read/Write Input BW0–BW1 Synchronous Byte Writes Input Active Low K Input Clock Input Active High C Output Clock Input Active High TMS Test Mode Select Input — TDI Test Data Input Input — TCK Test Clock Input Input — TDO Test Data Output Output — VREF HSTL Input Reference Voltage Input — ZQ Output Impedance Matching Input Input — K Input Clock Input Active Low C Output Clock Output Active Low DOFF DLL Disable — Active Low LD Synchronous Load Pin — Active Low CQ Output Echo Clock Output Active Low CQ Output Echo Clock Output Active High D Synchronous Data Inputs Input Q Synchronous Data Outputs Output VDD Power Supply Supply 1.8 V Nominal VDDQ Isolated Output Buffer Supply Supply 1.8 or 1.5 V Nominal VSS Power Supply: Ground Supply — Notes: 1. C, C, K, or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD, output impedance is set to minimum value and it cannot be connected to ground or left uncon- nected. 3. NC = Not Connected to die or any other pin GS8182S18D-267/250/200/167 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.08a 8/2005 3/31 © 2003, GSI Technology Background Separate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control protocol like that offered on the SigmaCIO devices. Therefore, while SigmaQuad SRAMs allow a user to operate both data ports at the same time, they force alternating loads of read and write addresses. SigmaSIO SRAMs allow continuous loads of read or write addresses like SigmaCIO SRAMs, but in a separate I/O configuration. |
Аналогичный номер детали - GS8182S18GD-200I |
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Аналогичное описание - GS8182S18GD-200I |
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